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clk: rockchip: switch to using the new cpuclk type for armclk

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This adds the necessary soc-specific divider values and switches the armclk
to use the newly introduced cpuclk type.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
This commit is contained in:
Heiko Stuebner
2014-09-05 11:25:03 +02:00
parent f6fba5f696
commit 0e5bdb3f9f
2 changed files with 169 additions and 6 deletions
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71
drivers/clk/rockchip/clk-rk3288.c
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@@ -101,6 +101,70 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
{ /* sentinel */ },
};
#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
#define RK3288_DIV_ACLK_CORE_MP_SHIFT 4
#define RK3288_DIV_L2RAM_MASK 0x7
#define RK3288_DIV_L2RAM_SHIFT 0
#define RK3288_DIV_ATCLK_MASK 0x1f
#define RK3288_DIV_ATCLK_SHIFT 4
#define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f
#define RK3288_DIV_PCLK_DBGPRE_SHIFT 9
#define RK3288_CLKSEL0(_core_m0, _core_mp) \
{ \
.reg = RK3288_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
RK3288_DIV_ACLK_CORE_MP_SHIFT), \
}
#define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \
{ \
.reg = RK3288_CLKSEL_CON(37), \
.val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
RK3288_DIV_L2RAM_SHIFT) | \
HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
RK3288_DIV_ATCLK_SHIFT) | \
HIWORD_UPDATE(_pclk_dbg_pre, \
RK3288_DIV_PCLK_DBGPRE_MASK, \
RK3288_DIV_PCLK_DBGPRE_SHIFT), \
}
#define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
{ \
.prate = _prate, \
.divs = { \
RK3288_CLKSEL0(_core_m0, _core_mp), \
RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
};
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
.core_reg = RK3288_CLKSEL_CON(0),
.div_core_shift = 8,
.div_core_mask = 0x1f,
.mux_core_shift = 15,
};
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
@@ -166,8 +230,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "gpll_core", "gpll", 0,
RK3288_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
RK3288_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
@@ -739,6 +801,11 @@ static void __init rk3288_clk_init(struct device_node *np)
rockchip_clk_protect_critical(rk3288_critical_clocks,
ARRAY_SIZE(rk3288_critical_clocks));
rockchip_clk_register_armclk(ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3288_cpuclk_data, rk3288_cpuclk_rates,
ARRAY_SIZE(rk3288_cpuclk_rates));
rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
}