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drm/amd/display: Add Raven2 definitions in dc

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Add Raven2 definitions in the dc code

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bhawanpreet Lakha
2018-01-22 16:12:27 -05:00
committed by Alex Deucher
parent 760067769e
commit 0e3d73f1a4
9 changed files with 78 additions and 1 deletions
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5
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
View File

@@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
return true;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#endif
case DCE_VERSION_12_0:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;

7
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case FAMILY_RV:
dc_version = DCN_VERSION_1_0;
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_1_01;
#endif
break;
#endif
default:
@@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
#endif
res_pool = dcn10_create_resource_pool(
num_virtual_links, dc);
break;

7
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View File

@@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
case DCN_VERSION_1_0:
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
#endif
dce112_get_pix_clk_dividers_helper(clk_src,
pll_settings, pix_clk_params);
break;
@@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
case DCN_VERSION_1_0:
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
#endif
if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
pll_settings->use_external_clk;

36
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
DCN10_CLK_SRC_PLL1,
DCN10_CLK_SRC_PLL2,
DCN10_CLK_SRC_PLL3,
DCN10_CLK_SRC_TOTAL
DCN10_CLK_SRC_TOTAL,
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
#endif
};
/* begin *********************
@@ -1163,6 +1166,10 @@ static bool construct(
/* max pipe num for ASIC before check pipe fuses */
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
if (dc->ctx->dce_version == DCN_VERSION_1_01)
pool->base.pipe_count = 3;
#endif
dc->caps.max_video_width = 3840;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
@@ -1194,13 +1201,28 @@ static bool construct(
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL2,
&clk_src_regs[2], false);
#ifdef CONFIG_DRM_AMD_DC_DCN1_01
if (dc->ctx->dce_version == DCN_VERSION_1_0) {
pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL3,
&clk_src_regs[3], false);
}
#else
pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL3,
&clk_src_regs[3], false);
#endif
pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
if (dc->ctx->dce_version == DCN_VERSION_1_01)
pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
#endif
pool->base.dp_clock_source =
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_ID_DP_DTO,
@@ -1246,6 +1268,18 @@ static bool construct(
memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
if (dc->ctx->dce_version == DCN_VERSION_1_01) {
struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
struct dcn_ip_params *dcn_ip = dc->dcn_ip;
struct display_mode_lib *dml = &dc->dml;
dml->ip.max_num_dpp = 3;
/* TODO how to handle 23.84? */
dcn_soc->dram_clock_change_latency = 23;
dcn_ip->max_num_dpp = 3;
}
#endif
if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
dc->dcn_soc->urgent_latency = 3;
dc->debug.disable_dmcu = true;

5
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
View File

@@ -86,6 +86,11 @@ bool dal_hw_factory_init(
dal_hw_factory_dcn10_init(factory);
return true;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
dal_hw_factory_dcn10_init(factory);
return true;
#endif
default:
ASSERT_CRITICAL(false);

5
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
View File

@@ -83,6 +83,11 @@ bool dal_hw_translate_init(
dal_hw_translate_dcn10_init(translate);
return true;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
dal_hw_translate_dcn10_init(translate);
return true;
#endif
default:
BREAK_TO_DEBUGGER();

4
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
View File

@@ -96,6 +96,10 @@ struct i2caux *dal_i2caux_create(
return dal_i2caux_dcn10_create(ctx);
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
return dal_i2caux_dcn10_create(ctx);
#endif
default:
BREAK_TO_DEBUGGER();
return NULL;