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NET: nps_enet: replace use of cause register

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When interrupt is received we read directly from control
register for RX/TX instead of reading cause register
since this register fails to indicate TX done when
TX interrupt is "edge mode".

Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Noam Camus
2015-08-20 08:00:01 +03:00
committed by David S. Miller
parent 1728369e8c
commit 0dd20f3ce0
2 changed files with 5 additions and 24 deletions
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9
drivers/net/ethernet/ezchip/nps_enet.c
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@@ -211,12 +211,13 @@ static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
{
struct net_device *ndev = dev_instance;
struct nps_enet_priv *priv = netdev_priv(ndev);
struct nps_enet_buf_int_cause buf_int_cause;
struct nps_enet_rx_ctl rx_ctrl;
struct nps_enet_tx_ctl tx_ctrl;
buf_int_cause.value =
nps_enet_reg_get(priv, NPS_ENET_REG_BUF_INT_CAUSE);
rx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
tx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
if (buf_int_cause.tx_done || buf_int_cause.rx_rdy)
if ((!tx_ctrl.ct && priv->tx_packet_sent) || rx_ctrl.cr)
if (likely(napi_schedule_prep(&priv->napi))) {
nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
__napi_schedule(&priv->napi);