Merge branches 'acpi-x86', 'acpi-cppc' and 'acpi-soc'
* acpi-x86: x86: ACPI: make variable names clearer in acpi_parse_madt_lapic_entries() x86: ACPI: remove extraneous white space after semicolon * acpi-cppc: ACPI / CPPC: Support PCC with interrupt flag ACPI / CPPC: Add prefix cppc to cpudata structure name ACPI / CPPC: Add support for functional fixed hardware address ACPI / CPPC: Don't return on CPPC probe failure ACPI / CPPC: Allow build with ACPI_CPU_FREQ_PSS config ACPI / CPPC: check for error bit in PCC status field ACPI / CPPC: move all PCC related information into pcc_data ACPI / CPPC: add sysfs support to compute delivered performance ACPI / CPPC: set a non-zero value for transition_latency ACPI / CPPC: support for batching CPPC requests ACPI / CPPC: acquire pcc_lock only while accessing PCC subspace ACPI / CPPC: restructure read/writes for efficient sys mapped reg ops mailbox: pcc: Support HW-Reduced Communication Subspace type 2 * acpi-soc: ACPI / APD: constify local structures ACPI / APD: Add device HID for Vulcan SPI controller
This commit is contained in:
@@ -1,6 +1,7 @@
|
||||
obj-$(CONFIG_ACPI) += boot.o
|
||||
obj-$(CONFIG_ACPI_SLEEP) += sleep.o wakeup_$(BITS).o
|
||||
obj-$(CONFIG_ACPI_APEI) += apei.o
|
||||
obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_msr.o
|
||||
|
||||
ifneq ($(CONFIG_ACPI_PROCESSOR),)
|
||||
obj-y += cstate.o
|
||||
|
@@ -1031,8 +1031,8 @@ static int __init acpi_parse_madt_lapic_entries(void)
|
||||
return ret;
|
||||
}
|
||||
|
||||
x2count = madt_proc[0].count;
|
||||
count = madt_proc[1].count;
|
||||
count = madt_proc[0].count;
|
||||
x2count = madt_proc[1].count;
|
||||
}
|
||||
if (!count && !x2count) {
|
||||
printk(KERN_ERR PREFIX "No LAPIC entries present\n");
|
||||
@@ -1513,7 +1513,7 @@ void __init acpi_boot_table_init(void)
|
||||
* If acpi_disabled, bail out
|
||||
*/
|
||||
if (acpi_disabled)
|
||||
return;
|
||||
return;
|
||||
|
||||
/*
|
||||
* Initialize the ACPI boot-time table parser.
|
||||
|
58
arch/x86/kernel/acpi/cppc_msr.c
Normal file
58
arch/x86/kernel/acpi/cppc_msr.c
Normal file
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* cppc_msr.c: MSR Interface for CPPC
|
||||
* Copyright (c) 2016, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <acpi/cppc_acpi.h>
|
||||
#include <asm/msr.h>
|
||||
|
||||
/* Refer to drivers/acpi/cppc_acpi.c for the description of functions */
|
||||
|
||||
bool cpc_ffh_supported(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = rdmsrl_safe_on_cpu(cpunum, reg->address, val);
|
||||
if (!err) {
|
||||
u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
|
||||
reg->bit_offset);
|
||||
|
||||
*val &= mask;
|
||||
*val >>= reg->bit_offset;
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
|
||||
{
|
||||
u64 rd_val;
|
||||
int err;
|
||||
|
||||
err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val);
|
||||
if (!err) {
|
||||
u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,
|
||||
reg->bit_offset);
|
||||
|
||||
val <<= reg->bit_offset;
|
||||
val &= mask;
|
||||
rd_val &= ~mask;
|
||||
rd_val |= val;
|
||||
err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val);
|
||||
}
|
||||
return err;
|
||||
}
|
Reference in New Issue
Block a user