Merge tag 'media/v4.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab: - a new frontend driver for new ATSC devices: lgdt3306a - a new sensor driver: ov2659 - a new platform driver: xilinx - the m88ts2022 tuner driver was merged at ts2020 driver - the media controller gained experimental support for DVB and hybrid devices - lots of random cleanups, fixes and improvements on media drivers * tag 'media/v4.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (404 commits) [media] uvcvideo: add support for VIDIOC_QUERY_EXT_CTRL [media] uvcvideo: fix cropcap v4l2-compliance failure [media] media: omap3isp: remove unused clkdev [media] coda: Add tracing support [media] coda: drop dma_sync_single_for_device in coda_bitstream_queue [media] coda: fix fill bitstream errors in nonstreaming case [media] coda: call SEQ_END when the first queue is stopped [media] coda: fail to start streaming if userspace set invalid formats [media] coda: remove duplicate error messages for buffer allocations [media] coda: move parameter buffer in together with context buffer allocation [media] coda: allocate bitstream buffer from REQBUFS, size depends on the format [media] coda: allocate per-context buffers from REQBUFS [media] coda: use strlcpy instead of snprintf [media] coda: bitstream payload is unsigned [media] coda: fix double call to debugfs_remove [media] coda: check kasprintf return value in coda_open [media] coda: bitrate can only be set in kbps steps [media] v4l2-mem2mem: no need to initialize b in v4l2_m2m_next_buf and v4l2_m2m_buf_remove [media] s5p-mfc: set allow_zero_bytesused flag for vb2_queue_init [media] coda: set allow_zero_bytesused flag for vb2_queue_init ...
This commit is contained in:
@@ -447,5 +447,6 @@ header-y += wireless.h
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header-y += x25.h
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header-y += xattr.h
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header-y += xfrm.h
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header-y += xilinx-v4l2-controls.h
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header-y += zorro.h
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header-y += zorro_ids.h
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@@ -21,6 +21,8 @@
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#ifndef AM437X_VPFE_USER_H
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#define AM437X_VPFE_USER_H
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#include <linux/videodev2.h>
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enum vpfe_ccdc_data_size {
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VPFE_CCDC_DATA_16BITS = 0,
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VPFE_CCDC_DATA_15BITS,
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|
@@ -45,6 +45,7 @@
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#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007
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#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008
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#define MEDIA_BUS_FMT_RGB666_1X18 0x1009
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#define MEDIA_BUS_FMT_RBG888_1X24 0x100e
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#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015
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#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010
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#define MEDIA_BUS_FMT_BGR888_1X24 0x1013
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@@ -55,6 +56,7 @@
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#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
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#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
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#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
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#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
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/* YUV (including grey) - next is 0x2026 */
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#define MEDIA_BUS_FMT_Y8_1X8 0x2001
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@@ -73,6 +75,10 @@
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#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b
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#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c
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#define MEDIA_BUS_FMT_Y12_1X12 0x2013
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#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c
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#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d
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#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e
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#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f
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#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f
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#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010
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#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011
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@@ -82,17 +88,14 @@
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#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b
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#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d
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#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e
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#define MEDIA_BUS_FMT_VUY8_1X24 0x2024
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#define MEDIA_BUS_FMT_YUV8_1X24 0x2025
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#define MEDIA_BUS_FMT_YUV10_1X30 0x2016
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#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017
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#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c
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#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d
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#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e
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#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f
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#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020
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#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021
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#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022
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#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023
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#define MEDIA_BUS_FMT_YUV10_1X30 0x2016
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#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017
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/* Bayer - next is 0x3019 */
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#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001
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@@ -50,7 +50,14 @@ struct media_device_info {
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#define MEDIA_ENT_T_DEVNODE_V4L (MEDIA_ENT_T_DEVNODE + 1)
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#define MEDIA_ENT_T_DEVNODE_FB (MEDIA_ENT_T_DEVNODE + 2)
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#define MEDIA_ENT_T_DEVNODE_ALSA (MEDIA_ENT_T_DEVNODE + 3)
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#define MEDIA_ENT_T_DEVNODE_DVB (MEDIA_ENT_T_DEVNODE + 4)
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#define MEDIA_ENT_T_DEVNODE_DVB_FE (MEDIA_ENT_T_DEVNODE + 4)
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#define MEDIA_ENT_T_DEVNODE_DVB_DEMUX (MEDIA_ENT_T_DEVNODE + 5)
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#define MEDIA_ENT_T_DEVNODE_DVB_DVR (MEDIA_ENT_T_DEVNODE + 6)
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#define MEDIA_ENT_T_DEVNODE_DVB_CA (MEDIA_ENT_T_DEVNODE + 7)
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#define MEDIA_ENT_T_DEVNODE_DVB_NET (MEDIA_ENT_T_DEVNODE + 8)
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/* Legacy symbol. Use it to avoid userspace compilation breakages */
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#define MEDIA_ENT_T_DEVNODE_DVB MEDIA_ENT_T_DEVNODE_DVB_FE
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#define MEDIA_ENT_T_V4L2_SUBDEV (2 << MEDIA_ENT_TYPE_SHIFT)
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#define MEDIA_ENT_T_V4L2_SUBDEV_SENSOR (MEDIA_ENT_T_V4L2_SUBDEV + 1)
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@@ -59,6 +66,8 @@ struct media_device_info {
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/* A converter of analogue video to its digital representation. */
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#define MEDIA_ENT_T_V4L2_SUBDEV_DECODER (MEDIA_ENT_T_V4L2_SUBDEV + 4)
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#define MEDIA_ENT_T_V4L2_SUBDEV_TUNER (MEDIA_ENT_T_V4L2_SUBDEV + 5)
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#define MEDIA_ENT_FL_DEFAULT (1 << 0)
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struct media_entity_desc {
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@@ -78,17 +87,48 @@ struct media_entity_desc {
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struct {
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__u32 major;
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__u32 minor;
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} v4l;
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struct {
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__u32 major;
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__u32 minor;
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} fb;
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} dev;
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#if 1
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/*
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* TODO: this shouldn't have been added without
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* actual drivers that use this. When the first real driver
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* appears that sets this information, special attention
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* should be given whether this information is 1) enough, and
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* 2) can deal with udev rules that rename devices. The struct
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* dev would not be sufficient for this since that does not
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* contain the subdevice information. In addition, struct dev
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* can only refer to a single device, and not to multiple (e.g.
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* pcm and mixer devices).
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*
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* So for now mark this as a to do.
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*/
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struct {
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__u32 card;
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__u32 device;
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__u32 subdevice;
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} alsa;
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#endif
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#if 1
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/*
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* DEPRECATED: previous node specifications. Kept just to
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* avoid breaking compilation, but media_entity_desc.dev
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* should be used instead. In particular, alsa and dvb
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* fields below are wrong: for all devnodes, there should
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* be just major/minor inside the struct, as this is enough
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* to represent any devnode, no matter what type.
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*/
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struct {
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__u32 major;
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__u32 minor;
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} v4l;
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struct {
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__u32 major;
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__u32 minor;
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} fb;
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int dvb;
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#endif
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/* Sub-device specifications */
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/* Nothing needed yet */
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@@ -48,14 +48,15 @@
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.type = V4L2_DV_BT_656_1120, \
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V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
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13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
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V4L2_DV_BT_STD_CEA861, \
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V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_720X480P59_94 { \
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.type = V4L2_DV_BT_656_1120, \
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V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
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27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
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V4L2_DV_BT_STD_CEA861, 0) \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
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}
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/* Note: these are the nominal timings, for HDMI links this format is typically
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@@ -64,14 +65,15 @@
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.type = V4L2_DV_BT_656_1120, \
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V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
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13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
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V4L2_DV_BT_STD_CEA861, \
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V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_720X576P50 { \
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.type = V4L2_DV_BT_656_1120, \
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V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
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27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
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V4L2_DV_BT_STD_CEA861, 0) \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_1280X720P24 { \
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@@ -88,7 +90,7 @@
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V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
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V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
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74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
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V4L2_DV_BT_STD_CEA861, 0) \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_1280X720P30 { \
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@@ -96,7 +98,8 @@
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V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
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V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
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74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
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V4L2_DV_BT_STD_CEA861, \
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V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_1280X720P50 { \
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@@ -104,7 +107,7 @@
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V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
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V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
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74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
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V4L2_DV_BT_STD_CEA861, 0) \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_1280X720P60 { \
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@@ -112,7 +115,8 @@
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V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
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V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
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74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
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V4L2_DV_BT_STD_CEA861, \
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V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_1920X1080P24 { \
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@@ -120,7 +124,8 @@
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V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
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V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
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74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
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V4L2_DV_BT_STD_CEA861, \
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V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_1920X1080P25 { \
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@@ -128,7 +133,7 @@
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V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
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V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
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74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
|
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V4L2_DV_BT_STD_CEA861, 0) \
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
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}
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#define V4L2_DV_BT_CEA_1920X1080P30 { \
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@@ -136,7 +141,8 @@
|
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V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
|
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V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
|
||||
74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
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#define V4L2_DV_BT_CEA_1920X1080I50 { \
|
||||
@@ -144,7 +150,8 @@
|
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V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
|
||||
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
|
||||
74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
|
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V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
|
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V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_1920X1080P50 { \
|
||||
@@ -152,7 +159,7 @@
|
||||
V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
|
||||
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
|
||||
148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, 0) \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_1920X1080I60 { \
|
||||
@@ -161,7 +168,8 @@
|
||||
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
|
||||
74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | \
|
||||
V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_1920X1080P60 { \
|
||||
@@ -170,77 +178,83 @@
|
||||
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
|
||||
148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_3840X2160P24 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_3840X2160P25 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, 0) \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_3840X2160P30 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_3840X2160P50 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, 0) \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_3840X2160P60 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_4096X2160P24 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_4096X2160P25 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, 0) \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_4096X2160P30 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_4096X2160P50 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, 0) \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
#define V4L2_DV_BT_CEA_4096X2160P60 { \
|
||||
.type = V4L2_DV_BT_656_1120, \
|
||||
V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
|
||||
594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
|
||||
V4L2_DV_BT_STD_CEA861, \
|
||||
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
|
||||
}
|
||||
|
||||
|
||||
|
@@ -69,12 +69,14 @@ struct v4l2_subdev_crop {
|
||||
* @pad: pad number, as reported by the media API
|
||||
* @index: format index during enumeration
|
||||
* @code: format code (MEDIA_BUS_FMT_ definitions)
|
||||
* @which: format type (from enum v4l2_subdev_format_whence)
|
||||
*/
|
||||
struct v4l2_subdev_mbus_code_enum {
|
||||
__u32 pad;
|
||||
__u32 index;
|
||||
__u32 code;
|
||||
__u32 reserved[9];
|
||||
__u32 which;
|
||||
__u32 reserved[8];
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -82,6 +84,7 @@ struct v4l2_subdev_mbus_code_enum {
|
||||
* @pad: pad number, as reported by the media API
|
||||
* @index: format index during enumeration
|
||||
* @code: format code (MEDIA_BUS_FMT_ definitions)
|
||||
* @which: format type (from enum v4l2_subdev_format_whence)
|
||||
*/
|
||||
struct v4l2_subdev_frame_size_enum {
|
||||
__u32 index;
|
||||
@@ -91,7 +94,8 @@ struct v4l2_subdev_frame_size_enum {
|
||||
__u32 max_width;
|
||||
__u32 min_height;
|
||||
__u32 max_height;
|
||||
__u32 reserved[9];
|
||||
__u32 which;
|
||||
__u32 reserved[8];
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -113,6 +117,7 @@ struct v4l2_subdev_frame_interval {
|
||||
* @width: frame width in pixels
|
||||
* @height: frame height in pixels
|
||||
* @interval: frame interval in seconds
|
||||
* @which: format type (from enum v4l2_subdev_format_whence)
|
||||
*/
|
||||
struct v4l2_subdev_frame_interval_enum {
|
||||
__u32 index;
|
||||
@@ -121,7 +126,8 @@ struct v4l2_subdev_frame_interval_enum {
|
||||
__u32 width;
|
||||
__u32 height;
|
||||
struct v4l2_fract interval;
|
||||
__u32 reserved[9];
|
||||
__u32 which;
|
||||
__u32 reserved[8];
|
||||
};
|
||||
|
||||
/**
|
||||
|
@@ -268,9 +268,10 @@ enum v4l2_ycbcr_encoding {
|
||||
|
||||
enum v4l2_quantization {
|
||||
/*
|
||||
* The default for R'G'B' quantization is always full range. For
|
||||
* Y'CbCr the quantization is always limited range, except for
|
||||
* SYCC, XV601, XV709 or JPEG: those are full range.
|
||||
* The default for R'G'B' quantization is always full range, except
|
||||
* for the BT2020 colorspace. For Y'CbCr the quantization is always
|
||||
* limited range, except for COLORSPACE_JPEG, SYCC, XV601 or XV709:
|
||||
* those are full range.
|
||||
*/
|
||||
V4L2_QUANTIZATION_DEFAULT = 0,
|
||||
V4L2_QUANTIZATION_FULL_RANGE = 1,
|
||||
@@ -1187,6 +1188,12 @@ struct v4l2_bt_timings {
|
||||
exactly the same number of half-lines. Whether half-lines can be detected
|
||||
or used depends on the hardware. */
|
||||
#define V4L2_DV_FL_HALF_LINE (1 << 3)
|
||||
/* If set, then this is a Consumer Electronics (CE) video format. Such formats
|
||||
* differ from other formats (commonly called IT formats) in that if RGB
|
||||
* encoding is used then by default the RGB values use limited range (i.e.
|
||||
* use the range 16-235) as opposed to 0-255. All formats defined in CEA-861
|
||||
* except for the 640x480 format are CE formats. */
|
||||
#define V4L2_DV_FL_IS_CE_VIDEO (1 << 4)
|
||||
|
||||
/* A few useful defines to calculate the total blanking and frame sizes */
|
||||
#define V4L2_DV_BT_BLANKING_WIDTH(bt) \
|
||||
@@ -1456,6 +1463,7 @@ struct v4l2_querymenu {
|
||||
#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040
|
||||
#define V4L2_CTRL_FLAG_VOLATILE 0x0080
|
||||
#define V4L2_CTRL_FLAG_HAS_PAYLOAD 0x0100
|
||||
#define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE 0x0200
|
||||
|
||||
/* Query flags, to be ORed with the control ID */
|
||||
#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000
|
||||
@@ -1841,8 +1849,8 @@ struct v4l2_mpeg_vbi_fmt_ivtv {
|
||||
*/
|
||||
struct v4l2_plane_pix_format {
|
||||
__u32 sizeimage;
|
||||
__u16 bytesperline;
|
||||
__u16 reserved[7];
|
||||
__u32 bytesperline;
|
||||
__u16 reserved[6];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/**
|
||||
|
73
include/uapi/linux/xilinx-v4l2-controls.h
Normal file
73
include/uapi/linux/xilinx-v4l2-controls.h
Normal file
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Xilinx Controls Header
|
||||
*
|
||||
* Copyright (C) 2013-2015 Ideas on Board
|
||||
* Copyright (C) 2013-2015 Xilinx, Inc.
|
||||
*
|
||||
* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
|
||||
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __UAPI_XILINX_V4L2_CONTROLS_H__
|
||||
#define __UAPI_XILINX_V4L2_CONTROLS_H__
|
||||
|
||||
#include <linux/v4l2-controls.h>
|
||||
|
||||
#define V4L2_CID_XILINX_OFFSET 0xc000
|
||||
#define V4L2_CID_XILINX_BASE (V4L2_CID_USER_BASE + V4L2_CID_XILINX_OFFSET)
|
||||
|
||||
/*
|
||||
* Private Controls for Xilinx Video IPs
|
||||
*/
|
||||
|
||||
/*
|
||||
* Xilinx TPG Video IP
|
||||
*/
|
||||
|
||||
#define V4L2_CID_XILINX_TPG (V4L2_CID_USER_BASE + 0xc000)
|
||||
|
||||
/* Draw cross hairs */
|
||||
#define V4L2_CID_XILINX_TPG_CROSS_HAIRS (V4L2_CID_XILINX_TPG + 1)
|
||||
/* Enable a moving box */
|
||||
#define V4L2_CID_XILINX_TPG_MOVING_BOX (V4L2_CID_XILINX_TPG + 2)
|
||||
/* Mask out a color component */
|
||||
#define V4L2_CID_XILINX_TPG_COLOR_MASK (V4L2_CID_XILINX_TPG + 3)
|
||||
/* Enable a stuck pixel feature */
|
||||
#define V4L2_CID_XILINX_TPG_STUCK_PIXEL (V4L2_CID_XILINX_TPG + 4)
|
||||
/* Enable a noisy output */
|
||||
#define V4L2_CID_XILINX_TPG_NOISE (V4L2_CID_XILINX_TPG + 5)
|
||||
/* Enable the motion feature */
|
||||
#define V4L2_CID_XILINX_TPG_MOTION (V4L2_CID_XILINX_TPG + 6)
|
||||
/* Configure the motion speed of moving patterns */
|
||||
#define V4L2_CID_XILINX_TPG_MOTION_SPEED (V4L2_CID_XILINX_TPG + 7)
|
||||
/* The row of horizontal cross hair location */
|
||||
#define V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW (V4L2_CID_XILINX_TPG + 8)
|
||||
/* The colum of vertical cross hair location */
|
||||
#define V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN (V4L2_CID_XILINX_TPG + 9)
|
||||
/* Set starting point of sine wave for horizontal component */
|
||||
#define V4L2_CID_XILINX_TPG_ZPLATE_HOR_START (V4L2_CID_XILINX_TPG + 10)
|
||||
/* Set speed of the horizontal component */
|
||||
#define V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED (V4L2_CID_XILINX_TPG + 11)
|
||||
/* Set starting point of sine wave for vertical component */
|
||||
#define V4L2_CID_XILINX_TPG_ZPLATE_VER_START (V4L2_CID_XILINX_TPG + 12)
|
||||
/* Set speed of the vertical component */
|
||||
#define V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED (V4L2_CID_XILINX_TPG + 13)
|
||||
/* Moving box size */
|
||||
#define V4L2_CID_XILINX_TPG_BOX_SIZE (V4L2_CID_XILINX_TPG + 14)
|
||||
/* Moving box color */
|
||||
#define V4L2_CID_XILINX_TPG_BOX_COLOR (V4L2_CID_XILINX_TPG + 15)
|
||||
/* Upper limit count of generated stuck pixels */
|
||||
#define V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH (V4L2_CID_XILINX_TPG + 16)
|
||||
/* Noise level */
|
||||
#define V4L2_CID_XILINX_TPG_NOISE_GAIN (V4L2_CID_XILINX_TPG + 17)
|
||||
|
||||
#endif /* __UAPI_XILINX_V4L2_CONTROLS_H__ */
|
Reference in New Issue
Block a user