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MIPS: Alchemy: RTC counter clocksource / clockevent support.

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Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device.  As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.

If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
2008-12-21 09:26:23 +01:00
committed by Ralf Baechle
parent 779e7d41ad
commit 0c694de12b
5 changed files with 143 additions and 181 deletions
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16
arch/mips/alchemy/common/power.c
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@@ -85,7 +85,11 @@ static unsigned int sleep_static_memctlr[4][3];
#define SLEEP_TEST_TIMEOUT 1
#ifdef SLEEP_TEST_TIMEOUT
static int sleep_ticks;
void wakeup_counter0_set(int ticks);
static void wakeup_counter0_set(int ticks)
{
au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2);
au_sync();
}
#endif
static void save_core_regs(void)
@@ -183,7 +187,6 @@ static void restore_core_regs(void)
}
restore_au1xxx_intctl();
wakeup_counter0_adjust();
}
unsigned long suspend_mode;
@@ -411,6 +414,15 @@ static struct ctl_table pm_dir_table[] = {
*/
static int __init pm_init(void)
{
/* init TOY to tick at 1Hz. No need to wait for access bits
* since there's plenty of time between here and the first
* suspend cycle.
*/
if (au_readl(SYS_TOYTRIM) != 32767) {
au_writel(32767, SYS_TOYTRIM);
au_sync();
}
register_sysctl_table(pm_dir_table);
return 0;
}