Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King:
- An improvement from Ard Biesheuvel, who noted that the identity map
setup was taking a long time due to flush_cache_louis().
- Update a comment about dma_ops from Wolfram Sang.
- Remove use of "-p" with ld, where this flag has been a no-op since
2004.
- Remove the printing of the virtual memory layout, which is no longer
useful since we hide pointers.
- Correct SCU help text.
- Remove legacy TWD registration method.
- Add pgprot_device() implementation for mapping PCI sysfs resource
files.
- Initialise PFN limits earlier for kmemleak.
- Fix argument count to match macro definition (affects clang builds)
- Use unified assembler language almost everywhere for clang, and other
clang improvements (from Stefan Agner, Nathan Chancellor).
- Support security extension for noMMU and other noMMU cleanups (from
Vladimir Murzin).
- Remove unnecessary SMP bringup code (which was incorrectly copy'n'
pasted from the ARM platform implementations) and remove it from the
arch code to discourge further copys of it appearing.
- Add Cortex A9 erratum preventing kexec working on some SoCs.
- AMBA bus identification updates from Mike Leach.
- More use of raw spinlocks to avoid -RT kernel issues (from Yang Shi
and Sebastian Andrzej Siewior).
- MCPM hyp/svc mode mismatch fixes from Marek Szyprowski.
* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (32 commits)
ARM: 8849/1: NOMMU: Fix encodings for PMSAv8's PRBAR4/PRLAR4
ARM: 8848/1: virt: Align GIC version check with arm64 counterpart
ARM: 8847/1: pm: fix HYP/SVC mode mismatch when MCPM is used
ARM: 8845/1: use unified assembler in c files
ARM: 8844/1: use unified assembler in assembly files
ARM: 8843/1: use unified assembler in headers
ARM: 8841/1: use unified assembler in macros
ARM: 8840/1: use a raw_spinlock_t in unwind
ARM: 8839/1: kprobe: make patch_lock a raw_spinlock_t
ARM: 8837/1: coresight: etmv4: Update ID register table to add UCI support
ARM: 8836/1: drivers: amba: Update component matching to use the CoreSight UCI values.
ARM: 8838/1: drivers: amba: Updates to component identification for driver matching.
ARM: 8833/1: Ensure that NEON code always compiles with Clang
ARM: avoid Cortex-A9 livelock on tight dmb loops
ARM: smp: remove arch-provided "pen_release"
ARM: actions: remove boot_lock and pen_release
ARM: oxnas: remove CPU hotplug implementation
ARM: qcom: remove unnecessary boot_lock
ARM: 8832/1: NOMMU: Limit visibility for CONFIG_FLASH_{MEM_BASE,SIZE}
ARM: 8831/1: NOMMU: pmsa-v8: remove unneeded semicolon
...
此提交包含在：
Linus Torvalds
@@ -376,9 +376,9 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
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.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
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9999:
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.if \inc == 1
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\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
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\instr\()b\t\cond\().w \reg, [\ptr, #\off]
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.elseif \inc == 4
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\instr\cond\()\t\().w \reg, [\ptr, #\off]
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\instr\t\cond\().w \reg, [\ptr, #\off]
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.else
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.error "Unsupported inc macro argument"
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.endif
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@@ -417,9 +417,9 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
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.rept \rept
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9999:
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.if \inc == 1
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\instr\cond\()b\()\t \reg, [\ptr], #\inc
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\instr\()b\t\cond \reg, [\ptr], #\inc
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.elseif \inc == 4
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\instr\cond\()\t \reg, [\ptr], #\inc
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\instr\t\cond \reg, [\ptr], #\inc
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.else
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.error "Unsupported inc macro argument"
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.endif
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@@ -460,7 +460,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
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.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
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#ifndef CONFIG_CPU_USE_DOMAINS
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adds \tmp, \addr, #\size - 1
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sbcccs \tmp, \tmp, \limit
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sbcscc \tmp, \tmp, \limit
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bcs \bad
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#ifdef CONFIG_CPU_SPECTRE
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movcs \addr, #0
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@@ -474,7 +474,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
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sub \tmp, \limit, #1
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subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
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addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
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subhss \tmp, \tmp, \size @ tmp = limit - (addr + size) }
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subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) }
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movlo \addr, #0 @ if (tmp < 0) addr = NULL
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csdb
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#endif
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@@ -11,6 +11,8 @@
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#define sev() __asm__ __volatile__ ("sev" : : : "memory")
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#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
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#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
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#else
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#define wfe() do { } while (0)
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#endif
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#if __LINUX_ARM_ARCH__ >= 7
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@@ -16,25 +16,25 @@
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ldr \tmp, =irq_prio_h
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teq \irqstat, #0
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#ifdef IOMD_BASE
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ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma
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ldrbeq \irqstat, [\base, #IOMD_DMAREQ] @ get dma
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addeq \tmp, \tmp, #256 @ irq_prio_h table size
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teqeq \irqstat, #0
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bne 2406f
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#endif
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ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
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ldrbeq \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
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addeq \tmp, \tmp, #256 @ irq_prio_d table size
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teqeq \irqstat, #0
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#ifdef IOMD_IRQREQC
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ldreqb \irqstat, [\base, #IOMD_IRQREQC]
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ldrbeq \irqstat, [\base, #IOMD_IRQREQC]
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addeq \tmp, \tmp, #256 @ irq_prio_l table size
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teqeq \irqstat, #0
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#endif
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#ifdef IOMD_IRQREQD
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ldreqb \irqstat, [\base, #IOMD_IRQREQD]
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ldrbeq \irqstat, [\base, #IOMD_IRQREQD]
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addeq \tmp, \tmp, #256 @ irq_prio_lc table size
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teqeq \irqstat, #0
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#endif
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2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number
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2406: ldrbne \irqnr, [\tmp, \irqstat] @ get IRQ number
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.endm
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/*
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@@ -125,6 +125,9 @@ extern pgprot_t pgprot_s2_device;
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#define pgprot_stronglyordered(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
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#define pgprot_device(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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#define pgprot_dmacoherent(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
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@@ -89,7 +89,11 @@ extern void release_thread(struct task_struct *);
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unsigned long get_wchan(struct task_struct *p);
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#if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
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#define cpu_relax() smp_mb()
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#define cpu_relax() \
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do { \
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smp_mb(); \
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__asm__ __volatile__("nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;"); \
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} while (0)
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#else
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#define cpu_relax() barrier()
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#endif
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@@ -67,7 +67,6 @@ struct secondary_data {
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void *stack;
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};
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extern struct secondary_data secondary_data;
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extern volatile int pen_release;
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extern void secondary_startup(void);
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extern void secondary_startup_arm(void);
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@@ -19,20 +19,4 @@
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#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
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#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
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#include <linux/ioport.h>
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struct twd_local_timer {
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struct resource res[2];
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};
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#define DEFINE_TWD_LOCAL_TIMER(name,base,irq) \
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struct twd_local_timer name __initdata = { \
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.res = { \
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DEFINE_RES_MEM(base, 0x10), \
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DEFINE_RES_IRQ(irq), \
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}, \
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};
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int twd_local_timer_register(struct twd_local_timer *);
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#endif
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@@ -210,11 +210,12 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
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prefetchw(&rw->lock);
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__asm__ __volatile__(
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" .syntax unified\n"
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"1: ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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WFE("mi")
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" rsbpls %0, %1, #0\n"
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" rsbspl %0, %1, #0\n"
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" bmi 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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@@ -10,6 +10,7 @@ struct sleep_save_sp {
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};
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extern void cpu_resume(void);
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extern void cpu_resume_no_hyp(void);
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extern void cpu_resume_arm(void);
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extern int cpu_suspend(unsigned long, int (*)(unsigned long));
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@@ -85,7 +85,8 @@ static inline void set_fs(mm_segment_t fs)
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#define __range_ok(addr, size) ({ \
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unsigned long flag, roksum; \
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__chk_user_ptr(addr); \
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__asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \
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__asm__(".syntax unified\n" \
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"adds %1, %2, %3; sbcscc %1, %1, %0; movcc %0, #0" \
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: "=&r" (flag), "=&r" (roksum) \
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: "r" (addr), "Ir" (size), "0" (current_thread_info()->addr_limit) \
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: "cc"); \
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@@ -49,7 +49,7 @@
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* (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
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*/
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#define EXC_RET_STACK_MASK 0x00000004
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#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
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#define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2)
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/* Cache related definitions */
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@@ -29,13 +29,13 @@
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ldr \tmp, =elf_hwcap @ may not have MVFR regs
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ldr \tmp, [\tmp, #0]
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tst \tmp, #HWCAP_VFPD32
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ldcnel p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
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ldclne p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
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addeq \base, \base, #32*4 @ step over unused register space
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#else
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
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ldcleq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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#endif
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@@ -53,13 +53,13 @@
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ldr \tmp, =elf_hwcap @ may not have MVFR regs
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ldr \tmp, [\tmp, #0]
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tst \tmp, #HWCAP_VFPD32
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stcnel p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
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stclne p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
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addeq \base, \base, #32*4 @ step over unused register space
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#else
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
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stcleq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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#endif
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