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Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Browse Source 
Pull media updates from Mauro Carvalho Chehab:
 "The first part of the media updates for Kernel 3.7.

  This series contain:

   - A major tree renaming patch series: now, drivers are organized
     internally by their used bus, instead of by V4L2 and/or DVB API,
     providing a cleaner driver location for hybrid drivers that
     implement both APIs, and allowing to cleanup the Kconfig items and
     make them more intuitive for the end user;

   - Media Kernel developers are typically very lazy with their duties
     of keeping the MAINTAINERS entries for their drivers updated.  As
     now the tree is more organized, we're doing an effort to add/update
     those entries for the drivers that aren't currently orphan;

   - Several DVB USB drivers got moved to a new DVB USB v2 core; the new
     core fixes several bugs (as the existing one that got bitroted).
     Now, suspend/resume finally started to work fine (at least with
     some devices - we should expect more work with regards to it);

   - added multistream support for DVB-T2, and unified the API for
     DVB-S2 and ISDB-S.  Backward binary support is preserved;

   - as usual, a few new drivers, some V4L2 core improvements and lots
     of drivers improvements and fixes.

  There are some points to notice on this series:

   1) you should expect a trivial merge conflict on your tree, with the
      removal of Documentation/feature-removal-schedule.txt: this series
      would be adding two additional entries there.  I opted to not
      rebase it due to this recent change;

   2) With regards to the PCTV 520e udev-related breakage, I opted to
      fix it in a way that the patches can be backported to 3.5 even
      without your firmware fix patch.  This way, Greg doesn't need to
      rush backporting your patch (as there are still the firmware cache
      and firmware path customization issues to be addressed there).

      I'll send later a patch (likely after the end of the merge window)
      reverting the rest of the DRX-K async firmware request, fully
      restoring its original behaviour to allow media drivers to
      initialize everything serialized as before for 3.7 and upper.

   3) I'm planning to work on this weekend to test the DMABUF patches
      for V4L2.  The patches are on my queue for several Kernel cycles,
      but, up to now, there is/was no way to test the series locally.

      I have some concerns about this particular changeset with regards
      to security issues, and with regards to the replacement of the old
      VIDIOC_OVERLAY ioctl's that is broken on modern systems, due to
      GPU drivers change.  The Overlay API allows direct PCI2PCI
      transfers from a media capture card into the GPU framebuffer, but
      its API is crappy.  Also, the only existing X11 driver that
      implements it requires a XV extension that is not available
      anymore on modern drivers.  The DMABUF can do the same thing, but
      with it is promising to be a properly-designed API.  If I can
      successfully test this series and be happy with it, I should be
      asking you to pull them next week."

* 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (717 commits)
  em28xx: regression fix: use DRX-K sync firmware requests on em28xx
  drxk: allow loading firmware synchrousnously
  em28xx: Make all em28xx extensions to be initialized asynchronously
  [media] tda18271: properly report read errors in tda18271_get_id
  [media] tda18271: delay IR & RF calibration until init() if delay_cal is set
  [media] MAINTAINERS: add Michael Krufky as tda827x maintainer
  [media] MAINTAINERS: add Michael Krufky as tda8290 maintainer
  [media] MAINTAINERS: add Michael Krufky as cxusb maintainer
  [media] MAINTAINERS: add Michael Krufky as lg2160 maintainer
  [media] MAINTAINERS: add Michael Krufky as lgdt3305 maintainer
  [media] MAINTAINERS: add Michael Krufky as mxl111sf maintainer
  [media] MAINTAINERS: add Michael Krufky as mxl5007t maintainer
  [media] MAINTAINERS: add Michael Krufky as tda18271 maintainer
  [media] s5p-tv: Report only multi-plane capabilities in vidioc_querycap
  [media] s5p-mfc: Fix misplaced return statement in s5p_mfc_suspend()
  [media] exynos-gsc: Add missing static storage class specifiers
  [media] exynos-gsc: Remove <linux/version.h> header file inclusion
  [media] s5p-fimc: Fix incorrect condition in fimc_lite_reqbufs()
  [media] s5p-tv: Fix potential NULL pointer dereference error
  [media] s5k6aa: Fix possible NULL pointer dereference
  ...
This commit is contained in:
Linus Torvalds
2012-10-07 17:49:05 +09:00
parent 7f60ba388f bd0d104988
commit 0b8e74c6f4
1670 changed files with 39103 additions and 26584 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/media/platform/omap3isp/Makefile Normal file
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# Makefile for OMAP3 ISP driver
ccflags-$(CONFIG_VIDEO_OMAP3_DEBUG) += -DDEBUG
omap3-isp-objs += \
isp.o ispqueue.o ispvideo.o \
ispcsiphy.o ispccp2.o ispcsi2.o \
ispccdc.o isppreview.o ispresizer.o \
ispstat.o isph3a_aewb.o isph3a_af.o isphist.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3-isp.o

61
drivers/media/platform/omap3isp/cfa_coef_table.h Normal file
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@@ -0,0 +1,61 @@
/*
* cfa_coef_table.h
*
* TI OMAP3 ISP - CFA coefficients table
*
* Copyright (C) 2009-2010 Nokia Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
{ 244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248,
244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248,
244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248 },
{ 0, 247, 0, 244, 247, 36, 27, 12, 0, 27, 0, 250, 244, 12, 250, 4,
0, 0, 0, 248, 0, 0, 40, 0, 4, 250, 12, 244, 250, 0, 27, 0,
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0, 247, 0, 244, 247, 36, 27, 12, 0, 27, 0, 250, 244, 12, 250, 4,
0, 0, 0, 248, 0, 0, 40, 0, 4, 250, 12, 244, 250, 0, 27, 0,
12, 27, 36, 247, 244, 0, 247, 0, 0, 40, 0, 0, 248, 0, 0, 0,
0, 247, 0, 244, 247, 36, 27, 12, 0, 27, 0, 250, 244, 12, 250, 4,
0, 0, 0, 248, 0, 0, 40, 0, 4, 250, 12, 244, 250, 0, 27, 0,
12, 27, 36, 247, 244, 0, 247, 0, 0, 40, 0, 0, 248, 0, 0, 0 },
{ 4, 250, 12, 244, 250, 0, 27, 0, 12, 27, 36, 247, 244, 0, 247, 0,
0, 0, 0, 248, 0, 0, 40, 0, 0, 247, 0, 244, 247, 36, 27, 12,
0, 27, 0, 250, 244, 12, 250, 4, 0, 40, 0, 0, 248, 0, 0, 0,
4, 250, 12, 244, 250, 0, 27, 0, 12, 27, 36, 247, 244, 0, 247, 0,
0, 0, 0, 248, 0, 0, 40, 0, 0, 247, 0, 244, 247, 36, 27, 12,
0, 27, 0, 250, 244, 12, 250, 4, 0, 40, 0, 0, 248, 0, 0, 0,
4, 250, 12, 244, 250, 0, 27, 0, 12, 27, 36, 247, 244, 0, 247, 0,
0, 0, 0, 248, 0, 0, 40, 0, 0, 247, 0, 244, 247, 36, 27, 12,
0, 27, 0, 250, 244, 12, 250, 4, 0, 40, 0, 0, 248, 0, 0, 0 },
{ 244,12, 250, 4, 0, 27, 0, 250, 247, 36, 27, 12, 0, 247, 0, 244,
248, 0, 0, 0, 0, 40, 0, 0, 244, 0, 247, 0, 12, 27, 36, 247,
250, 0, 27, 0, 4, 250, 12, 244, 0, 0, 40, 0, 0, 0, 0, 248,
244, 12, 250, 4, 0, 27, 0, 250, 247, 36, 27, 12, 0, 247, 0, 244,
248, 0, 0, 0, 0, 40, 0, 0, 244, 0, 247, 0, 12, 27, 36, 247,
250, 0, 27, 0, 4, 250, 12, 244, 0, 0, 40, 0, 0, 0, 0, 248,
244, 12, 250, 4, 0, 27, 0, 250, 247, 36, 27, 12, 0, 247, 0, 244,
248, 0, 0, 0, 0, 40, 0, 0, 244, 0, 247, 0, 12, 27, 36, 247,
250, 0, 27, 0, 4, 250, 12, 244, 0, 0, 40, 0, 0, 0, 0, 248 },

90
drivers/media/platform/omap3isp/gamma_table.h Normal file
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@@ -0,0 +1,90 @@
/*
* gamma_table.h
*
* TI OMAP3 ISP - Default gamma table for all components
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
0, 0, 1, 2, 3, 3, 4, 5, 6, 8, 10, 12, 14, 16, 18, 20,
22, 23, 25, 26, 28, 29, 31, 32, 34, 35, 36, 37, 39, 40, 41, 42,
43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 52, 53, 54, 55, 56, 57,
58, 59, 60, 61, 62, 63, 63, 64, 65, 66, 66, 67, 68, 69, 69, 70,
71, 72, 72, 73, 74, 75, 75, 76, 77, 78, 78, 79, 80, 81, 81, 82,
83, 84, 84, 85, 86, 87, 88, 88, 89, 90, 91, 91, 92, 93, 94, 94,
95, 96, 97, 97, 98, 98, 99, 99, 100, 100, 101, 101, 102, 103, 104, 104,
105, 106, 107, 108, 108, 109, 110, 111, 111, 112, 113, 114, 114, 115, 116, 117,
117, 118, 119, 119, 120, 120, 121, 121, 122, 122, 123, 123, 124, 124, 125, 125,
126, 126, 127, 127, 128, 128, 129, 129, 130, 130, 131, 131, 132, 132, 133, 133,
134, 134, 135, 135, 136, 136, 137, 137, 138, 138, 139, 139, 140, 140, 141, 141,
142, 142, 143, 143, 144, 144, 145, 145, 146, 146, 147, 147, 148, 148, 149, 149,
150, 150, 151, 151, 152, 152, 153, 153, 153, 153, 154, 154, 154, 154, 155, 155,
156, 156, 157, 157, 158, 158, 158, 159, 159, 159, 160, 160, 160, 161, 161, 162,
162, 163, 163, 164, 164, 164, 164, 165, 165, 165, 165, 166, 166, 167, 167, 168,
168, 169, 169, 170, 170, 170, 170, 171, 171, 171, 171, 172, 172, 173, 173, 174,
174, 175, 175, 176, 176, 176, 176, 177, 177, 177, 177, 178, 178, 178, 178, 179,
179, 179, 179, 180, 180, 180, 180, 181, 181, 181, 181, 182, 182, 182, 182, 183,
183, 183, 183, 184, 184, 184, 184, 185, 185, 185, 185, 186, 186, 186, 186, 187,
187, 187, 187, 188, 188, 188, 188, 189, 189, 189, 189, 190, 190, 190, 190, 191,
191, 191, 191, 192, 192, 192, 192, 193, 193, 193, 193, 194, 194, 194, 194, 195,
195, 195, 195, 196, 196, 196, 196, 197, 197, 197, 197, 198, 198, 198, 198, 199,
199, 199, 199, 200, 200, 200, 200, 201, 201, 201, 201, 202, 202, 202, 203, 203,
203, 203, 204, 204, 204, 204, 205, 205, 205, 205, 206, 206, 206, 206, 207, 207,
207, 207, 208, 208, 208, 208, 209, 209, 209, 209, 210, 210, 210, 210, 210, 210,
210, 210, 210, 210, 210, 210, 211, 211, 211, 211, 211, 211, 211, 211, 211, 211,
211, 212, 212, 212, 212, 213, 213, 213, 213, 213, 213, 213, 213, 213, 213, 213,
213, 214, 214, 214, 214, 215, 215, 215, 215, 215, 215, 215, 215, 215, 215, 215,
216, 216, 216, 216, 217, 217, 217, 217, 218, 218, 218, 218, 219, 219, 219, 219,
219, 219, 219, 219, 219, 219, 219, 219, 220, 220, 220, 220, 221, 221, 221, 221,
221, 221, 221, 221, 221, 221, 221, 222, 222, 222, 222, 223, 223, 223, 223, 223,
223, 223, 223, 223, 223, 223, 223, 224, 224, 224, 224, 225, 225, 225, 225, 225,
225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 226, 226,
226, 226, 227, 227, 227, 227, 227, 227, 227, 227, 227, 227, 227, 227, 228, 228,
228, 229, 229, 229, 229, 229, 229, 229, 229, 229, 229, 229, 229, 230, 230, 230,
230, 231, 231, 231, 231, 231, 231, 231, 231, 231, 231, 231, 231, 232, 232, 232,
232, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232, 232,
233, 233, 233, 233, 234, 234, 234, 234, 234, 234, 234, 234, 234, 234, 234, 235,
235, 235, 235, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
236, 236, 236, 236, 236, 236, 237, 237, 237, 237, 238, 238, 238, 238, 238, 238,
238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238, 238,
238, 238, 238, 238, 238, 239, 239, 239, 239, 240, 240, 240, 240, 240, 240, 240,
240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240,
240, 240, 240, 240, 241, 241, 241, 241, 242, 242, 242, 242, 242, 242, 242, 242,
242, 242, 242, 242, 242, 242, 242, 242, 242, 242, 242, 242, 242, 242, 242, 242,
242, 242, 243, 243, 243, 243, 244, 244, 244, 244, 244, 244, 244, 244, 244, 244,
244, 244, 244, 244, 244, 244, 244, 244, 244, 244, 244, 244, 244, 244, 244, 244,
244, 245, 245, 245, 245, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
246, 246, 246, 246, 246, 246, 246, 247, 247, 247, 247, 248, 248, 248, 248, 248,
248, 248, 248, 248, 248, 248, 248, 248, 248, 248, 248, 248, 248, 248, 248, 248,
248, 248, 248, 248, 248, 248, 249, 249, 249, 249, 250, 250, 250, 250, 250, 250,
250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250,
250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250,
250, 250, 250, 250, 251, 251, 251, 251, 252, 252, 252, 252, 252, 252, 252, 252,
252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252,
252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252,
252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252,
252, 252, 252, 252, 252, 252, 252, 252, 253, 253, 253, 253, 253, 253, 253, 253,
253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253,
253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253,
253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253, 253,
253, 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,

2245
drivers/media/platform/omap3isp/isp.c Normal file
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File diff suppressed because it is too large Load Diff

352
drivers/media/platform/omap3isp/isp.h Normal file
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@@ -0,0 +1,352 @@
/*
* isp.h
*
* TI OMAP3 ISP - Core
*
* Copyright (C) 2009-2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_CORE_H
#define OMAP3_ISP_CORE_H
#include <media/omap3isp.h>
#include <media/v4l2-device.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/wait.h>
#include <linux/iommu.h>
#include <plat/iommu.h>
#include <plat/iovmm.h>
#include "ispstat.h"
#include "ispccdc.h"
#include "ispreg.h"
#include "ispresizer.h"
#include "isppreview.h"
#include "ispcsiphy.h"
#include "ispcsi2.h"
#include "ispccp2.h"
#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
#define ISP_TOK_TERM 0xFFFFFFFF /*
* terminating token for ISP
* modules reg list
*/
#define to_isp_device(ptr_module) \
container_of(ptr_module, struct isp_device, isp_##ptr_module)
#define to_device(ptr_module) \
(to_isp_device(ptr_module)->dev)
enum isp_mem_resources {
OMAP3_ISP_IOMEM_MAIN,
OMAP3_ISP_IOMEM_CCP2,
OMAP3_ISP_IOMEM_CCDC,
OMAP3_ISP_IOMEM_HIST,
OMAP3_ISP_IOMEM_H3A,
OMAP3_ISP_IOMEM_PREV,
OMAP3_ISP_IOMEM_RESZ,
OMAP3_ISP_IOMEM_SBL,
OMAP3_ISP_IOMEM_CSI2A_REGS1,
OMAP3_ISP_IOMEM_CSIPHY2,
OMAP3_ISP_IOMEM_CSI2A_REGS2,
OMAP3_ISP_IOMEM_CSI2C_REGS1,
OMAP3_ISP_IOMEM_CSIPHY1,
OMAP3_ISP_IOMEM_CSI2C_REGS2,
OMAP3_ISP_IOMEM_LAST
};
enum isp_sbl_resource {
OMAP3_ISP_SBL_CSI1_READ = 0x1,
OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
OMAP3_ISP_SBL_RESIZER_READ = 0x100,
OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
};
enum isp_subclk_resource {
OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
OMAP3_ISP_SUBCLK_AEWB = (1 << 1),
OMAP3_ISP_SUBCLK_AF = (1 << 2),
OMAP3_ISP_SUBCLK_HIST = (1 << 3),
OMAP3_ISP_SUBCLK_PREVIEW = (1 << 4),
OMAP3_ISP_SUBCLK_RESIZER = (1 << 5),
};
/* ISP: OMAP 34xx ES 1.0 */
#define ISP_REVISION_1_0 0x10
/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
#define ISP_REVISION_2_0 0x20
/* ISP2P: OMAP 36xx */
#define ISP_REVISION_15_0 0xF0
/*
* struct isp_res_mapping - Map ISP io resources to ISP revision.
* @isp_rev: ISP_REVISION_x_x
* @map: bitmap for enum isp_mem_resources
*/
struct isp_res_mapping {
u32 isp_rev;
u32 map;
};
/*
* struct isp_reg - Structure for ISP register values.
* @reg: 32-bit Register address.
* @val: 32-bit Register value.
*/
struct isp_reg {
enum isp_mem_resources mmio_range;
u32 reg;
u32 val;
};
struct isp_platform_callback {
u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
int (*csiphy_config)(struct isp_csiphy *phy,
struct isp_csiphy_dphy_cfg *dphy,
struct isp_csiphy_lanes_cfg *lanes);
};
/*
* struct isp_device - ISP device structure.
* @dev: Device pointer specific to the OMAP3 ISP.
* @revision: Stores current ISP module revision.
* @irq_num: Currently used IRQ number.
* @mmio_base: Array with kernel base addresses for ioremapped ISP register
* regions.
* @mmio_base_phys: Array with physical L4 bus addresses for ISP register
* regions.
* @mmio_size: Array with ISP register regions size in bytes.
* @raw_dmamask: Raw DMA mask
* @stat_lock: Spinlock for handling statistics
* @isp_mutex: Mutex for serializing requests to ISP.
* @crashed: Bitmask of crashed entities (indexed by entity ID)
* @has_context: Context has been saved at least once and can be restored.
* @ref_count: Reference count for handling multiple ISP requests.
* @cam_ick: Pointer to camera interface clock structure.
* @cam_mclk: Pointer to camera functional clock structure.
* @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
* @irq: Currently attached ISP ISR callbacks information structure.
* @isp_af: Pointer to current settings for ISP AutoFocus SCM.
* @isp_hist: Pointer to current settings for ISP Histogram SCM.
* @isp_h3a: Pointer to current settings for ISP Auto Exposure and
* White Balance SCM.
* @isp_res: Pointer to current settings for ISP Resizer.
* @isp_prev: Pointer to current settings for ISP Preview.
* @isp_ccdc: Pointer to current settings for ISP CCDC.
* @iommu: Pointer to requested IOMMU instance for ISP.
* @platform_cb: ISP driver callback function pointers for platform code
*
* This structure is used to store the OMAP ISP Information.
*/
struct isp_device {
struct v4l2_device v4l2_dev;
struct media_device media_dev;
struct device *dev;
u32 revision;
/* platform HW resources */
struct isp_platform_data *pdata;
unsigned int irq_num;
void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
u64 raw_dmamask;
/* ISP Obj */
spinlock_t stat_lock; /* common lock for statistic drivers */
struct mutex isp_mutex; /* For handling ref_count field */
u32 crashed;
int has_context;
int ref_count;
unsigned int autoidle;
u32 xclk_divisor[2]; /* Two clocks, a and b. */
#define ISP_CLK_CAM_ICK 0
#define ISP_CLK_CAM_MCLK 1
#define ISP_CLK_DPLL4_M5_CK 2
#define ISP_CLK_CSI2_FCK 3
#define ISP_CLK_L3_ICK 4
struct clk *clock[5];
/* ISP modules */
struct ispstat isp_af;
struct ispstat isp_aewb;
struct ispstat isp_hist;
struct isp_res_device isp_res;
struct isp_prev_device isp_prev;
struct isp_ccdc_device isp_ccdc;
struct isp_csi2_device isp_csi2a;
struct isp_csi2_device isp_csi2c;
struct isp_ccp2_device isp_ccp2;
struct isp_csiphy isp_csiphy1;
struct isp_csiphy isp_csiphy2;
unsigned int sbl_resources;
unsigned int subclk_resources;
struct iommu_domain *domain;
struct isp_platform_callback platform_cb;
};
#define v4l2_dev_to_isp_device(dev) \
container_of(dev, struct isp_device, v4l2_dev)
void omap3isp_hist_dma_done(struct isp_device *isp);
void omap3isp_flush(struct isp_device *isp);
int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
atomic_t *stopping);
int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
atomic_t *stopping);
int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
enum isp_pipeline_stream_state state);
void omap3isp_configure_bridge(struct isp_device *isp,
enum ccdc_input_entity input,
const struct isp_parallel_platform_data *pdata,
unsigned int shift, unsigned int bridge);
struct isp_device *omap3isp_get(struct isp_device *isp);
void omap3isp_put(struct isp_device *isp);
void omap3isp_print_status(struct isp_device *isp);
void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
void omap3isp_subclk_enable(struct isp_device *isp,
enum isp_subclk_resource res);
void omap3isp_subclk_disable(struct isp_device *isp,
enum isp_subclk_resource res);
int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
int omap3isp_register_entities(struct platform_device *pdev,
struct v4l2_device *v4l2_dev);
void omap3isp_unregister_entities(struct platform_device *pdev);
/*
* isp_reg_readl - Read value of an OMAP3 ISP register
* @dev: Device pointer specific to the OMAP3 ISP.
* @isp_mmio_range: Range to which the register offset refers to.
* @reg_offset: Register offset to read from.
*
* Returns an unsigned 32 bit value with the required register contents.
*/
static inline
u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
u32 reg_offset)
{
return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
}
/*
* isp_reg_writel - Write value to an OMAP3 ISP register
* @dev: Device pointer specific to the OMAP3 ISP.
* @reg_value: 32 bit value to write to the register.
* @isp_mmio_range: Range to which the register offset refers to.
* @reg_offset: Register offset to write into.
*/
static inline
void isp_reg_writel(struct isp_device *isp, u32 reg_value,
enum isp_mem_resources isp_mmio_range, u32 reg_offset)
{
__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
}
/*
* isp_reg_and - Clear individual bits in an OMAP3 ISP register
* @dev: Device pointer specific to the OMAP3 ISP.
* @mmio_range: Range to which the register offset refers to.
* @reg: Register offset to work on.
* @clr_bits: 32 bit value which would be cleared in the register.
*/
static inline
void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
u32 reg, u32 clr_bits)
{
u32 v = isp_reg_readl(isp, mmio_range, reg);
isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
}
/*
* isp_reg_set - Set individual bits in an OMAP3 ISP register
* @dev: Device pointer specific to the OMAP3 ISP.
* @mmio_range: Range to which the register offset refers to.
* @reg: Register offset to work on.
* @set_bits: 32 bit value which would be set in the register.
*/
static inline
void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
u32 reg, u32 set_bits)
{
u32 v = isp_reg_readl(isp, mmio_range, reg);
isp_reg_writel(isp, v | set_bits, mmio_range, reg);
}
/*
* isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
* @dev: Device pointer specific to the OMAP3 ISP.
* @mmio_range: Range to which the register offset refers to.
* @reg: Register offset to work on.
* @clr_bits: 32 bit value which would be cleared in the register.
* @set_bits: 32 bit value which would be set in the register.
*
* The clear operation is done first, and then the set operation.
*/
static inline
void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
u32 reg, u32 clr_bits, u32 set_bits)
{
u32 v = isp_reg_readl(isp, mmio_range, reg);
isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
}
static inline enum v4l2_buf_type
isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
{
if (pad >= subdev->entity.num_pads)
return 0;
if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
return V4L2_BUF_TYPE_VIDEO_OUTPUT;
else
return V4L2_BUF_TYPE_VIDEO_CAPTURE;
}
#endif /* OMAP3_ISP_CORE_H */

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/*
* ispccdc.h
*
* TI OMAP3 ISP - CCDC module
*
* Copyright (C) 2009-2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_CCDC_H
#define OMAP3_ISP_CCDC_H
#include <linux/omap3isp.h>
#include <linux/workqueue.h>
#include "ispvideo.h"
enum ccdc_input_entity {
CCDC_INPUT_NONE,
CCDC_INPUT_PARALLEL,
CCDC_INPUT_CSI2A,
CCDC_INPUT_CCP2B,
CCDC_INPUT_CSI2C
};
#define CCDC_OUTPUT_MEMORY (1 << 0)
#define CCDC_OUTPUT_PREVIEW (1 << 1)
#define CCDC_OUTPUT_RESIZER (1 << 2)
#define OMAP3ISP_CCDC_NEVENTS 16
enum ispccdc_lsc_state {
LSC_STATE_STOPPED = 0,
LSC_STATE_STOPPING = 1,
LSC_STATE_RUNNING = 2,
LSC_STATE_RECONFIG = 3,
};
struct ispccdc_lsc_config_req {
struct list_head list;
struct omap3isp_ccdc_lsc_config config;
unsigned char enable;
u32 table;
struct iovm_struct *iovm;
};
/*
* ispccdc_lsc - CCDC LSC parameters
* @update_config: Set when user changes config
* @request_enable: Whether LSC is requested to be enabled
* @config: LSC config set by user
* @update_table: Set when user provides a new LSC table to table_new
* @table_new: LSC table set by user, ISP address
* @table_inuse: LSC table currently in use, ISP address
*/
struct ispccdc_lsc {
enum ispccdc_lsc_state state;
struct work_struct table_work;
/* LSC queue of configurations */
spinlock_t req_lock;
struct ispccdc_lsc_config_req *request; /* requested configuration */
struct ispccdc_lsc_config_req *active; /* active configuration */
struct list_head free_queue; /* configurations for freeing */
};
#define CCDC_STOP_NOT_REQUESTED 0x00
#define CCDC_STOP_REQUEST 0x01
#define CCDC_STOP_EXECUTED (0x02 | CCDC_STOP_REQUEST)
#define CCDC_STOP_CCDC_FINISHED 0x04
#define CCDC_STOP_LSC_FINISHED 0x08
#define CCDC_STOP_FINISHED \
(CCDC_STOP_EXECUTED | CCDC_STOP_CCDC_FINISHED | CCDC_STOP_LSC_FINISHED)
#define CCDC_EVENT_VD1 0x10
#define CCDC_EVENT_VD0 0x20
#define CCDC_EVENT_LSC_DONE 0x40
/* Sink and source CCDC pads */
#define CCDC_PAD_SINK 0
#define CCDC_PAD_SOURCE_OF 1
#define CCDC_PAD_SOURCE_VP 2
#define CCDC_PADS_NUM 3
/*
* struct isp_ccdc_device - Structure for the CCDC module to store its own
* information
* @subdev: V4L2 subdevice
* @pads: Sink and source media entity pads
* @formats: Active video formats
* @crop: Active crop rectangle on the OF source pad
* @input: Active input
* @output: Active outputs
* @video_out: Output video node
* @alaw: A-law compression enabled (1) or disabled (0)
* @lpf: Low pass filter enabled (1) or disabled (0)
* @obclamp: Optical-black clamp enabled (1) or disabled (0)
* @fpc_en: Faulty pixels correction enabled (1) or disabled (0)
* @blcomp: Black level compensation configuration
* @clamp: Optical-black or digital clamp configuration
* @fpc: Faulty pixels correction configuration
* @lsc: Lens shading compensation configuration
* @update: Bitmask of controls to update during the next interrupt
* @shadow_update: Controls update in progress by userspace
* @underrun: A buffer underrun occurred and a new buffer has been queued
* @state: Streaming state
* @lock: Serializes shadow_update with interrupt handler
* @wait: Wait queue used to stop the module
* @stopping: Stopping state
* @ioctl_lock: Serializes ioctl calls and LSC requests freeing
*/
struct isp_ccdc_device {
struct v4l2_subdev subdev;
struct media_pad pads[CCDC_PADS_NUM];
struct v4l2_mbus_framefmt formats[CCDC_PADS_NUM];
struct v4l2_rect crop;
enum ccdc_input_entity input;
unsigned int output;
struct isp_video video_out;
unsigned int alaw:1,
lpf:1,
obclamp:1,
fpc_en:1;
struct omap3isp_ccdc_blcomp blcomp;
struct omap3isp_ccdc_bclamp clamp;
struct omap3isp_ccdc_fpc fpc;
struct ispccdc_lsc lsc;
unsigned int update;
unsigned int shadow_update;
unsigned int underrun:1;
enum isp_pipeline_stream_state state;
spinlock_t lock;
wait_queue_head_t wait;
unsigned int stopping;
struct mutex ioctl_lock;
};
struct isp_device;
int omap3isp_ccdc_init(struct isp_device *isp);
void omap3isp_ccdc_cleanup(struct isp_device *isp);
int omap3isp_ccdc_register_entities(struct isp_ccdc_device *ccdc,
struct v4l2_device *vdev);
void omap3isp_ccdc_unregister_entities(struct isp_ccdc_device *ccdc);
int omap3isp_ccdc_busy(struct isp_ccdc_device *isp_ccdc);
int omap3isp_ccdc_isr(struct isp_ccdc_device *isp_ccdc, u32 events);
void omap3isp_ccdc_restore_context(struct isp_device *isp);
void omap3isp_ccdc_max_rate(struct isp_ccdc_device *ccdc,
unsigned int *max_rate);
#endif /* OMAP3_ISP_CCDC_H */

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/*
* ispccp2.h
*
* TI OMAP3 ISP - CCP2 module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2010 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_CCP2_H
#define OMAP3_ISP_CCP2_H
#include <linux/videodev2.h>
struct isp_device;
struct isp_csiphy;
/* Sink and source ccp2 pads */
#define CCP2_PAD_SINK 0
#define CCP2_PAD_SOURCE 1
#define CCP2_PADS_NUM 2
/* CCP2 input media entity */
enum ccp2_input_entity {
CCP2_INPUT_NONE,
CCP2_INPUT_SENSOR,
CCP2_INPUT_MEMORY,
};
/* CCP2 output media entity */
enum ccp2_output_entity {
CCP2_OUTPUT_NONE,
CCP2_OUTPUT_CCDC,
CCP2_OUTPUT_MEMORY,
};
/* Logical channel configuration */
struct isp_interface_lcx_config {
int crc;
u32 data_start;
u32 data_size;
u32 format;
};
/* Memory channel configuration */
struct isp_interface_mem_config {
u32 dst_port;
u32 vsize_count;
u32 hsize_count;
u32 src_ofst;
u32 dst_ofst;
};
/* CCP2 device */
struct isp_ccp2_device {
struct v4l2_subdev subdev;
struct v4l2_mbus_framefmt formats[CCP2_PADS_NUM];
struct media_pad pads[CCP2_PADS_NUM];
enum ccp2_input_entity input;
enum ccp2_output_entity output;
struct isp_interface_lcx_config if_cfg;
struct isp_interface_mem_config mem_cfg;
struct isp_video video_in;
struct isp_csiphy *phy;
struct regulator *vdds_csib;
enum isp_pipeline_stream_state state;
wait_queue_head_t wait;
atomic_t stopping;
};
/* Function declarations */
int omap3isp_ccp2_init(struct isp_device *isp);
void omap3isp_ccp2_cleanup(struct isp_device *isp);
int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
struct v4l2_device *vdev);
void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2);
void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2);
#endif /* OMAP3_ISP_CCP2_H */

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/*
* ispcsi2.h
*
* TI OMAP3 ISP - CSI2 module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_CSI2_H
#define OMAP3_ISP_CSI2_H
#include <linux/types.h>
#include <linux/videodev2.h>
struct isp_csiphy;
/* This is not an exhaustive list */
enum isp_csi2_pix_formats {
CSI2_PIX_FMT_OTHERS = 0,
CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
CSI2_PIX_FMT_RAW8 = 0x2a,
CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
CSI2_PIX_FMT_RAW8_VP = 0x12a,
CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,
CSI2_USERDEF_8BIT_DATA1 = 0x40,
};
enum isp_csi2_irqevents {
OCP_ERR_IRQ = 0x4000,
SHORT_PACKET_IRQ = 0x2000,
ECC_CORRECTION_IRQ = 0x1000,
ECC_NO_CORRECTION_IRQ = 0x800,
COMPLEXIO2_ERR_IRQ = 0x400,
COMPLEXIO1_ERR_IRQ = 0x200,
FIFO_OVF_IRQ = 0x100,
CONTEXT7 = 0x80,
CONTEXT6 = 0x40,
CONTEXT5 = 0x20,
CONTEXT4 = 0x10,
CONTEXT3 = 0x8,
CONTEXT2 = 0x4,
CONTEXT1 = 0x2,
CONTEXT0 = 0x1,
};
enum isp_csi2_ctx_irqevents {
CTX_ECC_CORRECTION = 0x100,
CTX_LINE_NUMBER = 0x80,
CTX_FRAME_NUMBER = 0x40,
CTX_CS = 0x20,
CTX_LE = 0x8,
CTX_LS = 0x4,
CTX_FE = 0x2,
CTX_FS = 0x1,
};
enum isp_csi2_frame_mode {
ISP_CSI2_FRAME_IMMEDIATE,
ISP_CSI2_FRAME_AFTERFEC,
};
#define ISP_CSI2_MAX_CTX_NUM 7
struct isp_csi2_ctx_cfg {
u8 ctxnum; /* context number 0 - 7 */
u8 dpcm_decompress;
/* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */
u8 virtual_id;
u16 format_id; /* as in CSI2_CTx_CTRL2[9:0] */
u8 dpcm_predictor; /* 1: simple, 0: advanced */
/* Fields in CSI2_CTx_CTRL1/3 - Shadowed */
u16 alpha;
u16 data_offset;
u32 ping_addr;
u32 pong_addr;
u8 eof_enabled;
u8 eol_enabled;
u8 checksum_enabled;
u8 enabled;
};
struct isp_csi2_timing_cfg {
u8 ionum; /* IO1 or IO2 as in CSI2_TIMING */
unsigned force_rx_mode:1;
unsigned stop_state_16x:1;
unsigned stop_state_4x:1;
u16 stop_state_counter;
};
struct isp_csi2_ctrl_cfg {
bool vp_clk_enable;
bool vp_only_enable;
u8 vp_out_ctrl;
enum isp_csi2_frame_mode frame_mode;
bool ecc_enable;
bool if_enable;
};
#define CSI2_PAD_SINK 0
#define CSI2_PAD_SOURCE 1
#define CSI2_PADS_NUM 2
#define CSI2_OUTPUT_CCDC (1 << 0)
#define CSI2_OUTPUT_MEMORY (1 << 1)
struct isp_csi2_device {
struct v4l2_subdev subdev;
struct media_pad pads[CSI2_PADS_NUM];
struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
struct isp_video video_out;
struct isp_device *isp;
u8 available; /* Is the IP present on the silicon? */
/* mem resources - enums as defined in enum isp_mem_resources */
u8 regs1;
u8 regs2;
u32 output; /* output to CCDC, memory or both? */
bool dpcm_decompress;
unsigned int frame_skip;
struct isp_csiphy *phy;
struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1];
struct isp_csi2_timing_cfg timing[2];
struct isp_csi2_ctrl_cfg ctrl;
enum isp_pipeline_stream_state state;
wait_queue_head_t wait;
atomic_t stopping;
};
void omap3isp_csi2_isr(struct isp_csi2_device *csi2);
int omap3isp_csi2_reset(struct isp_csi2_device *csi2);
int omap3isp_csi2_init(struct isp_device *isp);
void omap3isp_csi2_cleanup(struct isp_device *isp);
void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2);
int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
struct v4l2_device *vdev);
#endif /* OMAP3_ISP_CSI2_H */

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/*
* ispcsiphy.c
*
* TI OMAP3 ISP - CSI PHY module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/regulator/consumer.h>
#include "isp.h"
#include "ispreg.h"
#include "ispcsiphy.h"
/*
* csiphy_lanes_config - Configuration of CSIPHY lanes.
*
* Updates HW configuration.
* Called with phy->mutex taken.
*/
static void csiphy_lanes_config(struct isp_csiphy *phy)
{
unsigned int i;
u32 reg;
reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG);
for (i = 0; i < phy->num_data_lanes; i++) {
reg &= ~(ISPCSI2_PHY_CFG_DATA_POL_MASK(i + 1) |
ISPCSI2_PHY_CFG_DATA_POSITION_MASK(i + 1));
reg |= (phy->lanes.data[i].pol <<
ISPCSI2_PHY_CFG_DATA_POL_SHIFT(i + 1));
reg |= (phy->lanes.data[i].pos <<
ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(i + 1));
}
reg &= ~(ISPCSI2_PHY_CFG_CLOCK_POL_MASK |
ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK);
reg |= phy->lanes.clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT;
reg |= phy->lanes.clk.pos << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT;
isp_reg_writel(phy->isp, reg, phy->cfg_regs, ISPCSI2_PHY_CFG);
}
/*
* csiphy_power_autoswitch_enable
* @enable: Sets or clears the autoswitch function enable flag.
*/
static void csiphy_power_autoswitch_enable(struct isp_csiphy *phy, bool enable)
{
isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,
ISPCSI2_PHY_CFG_PWR_AUTO,
enable ? ISPCSI2_PHY_CFG_PWR_AUTO : 0);
}
/*
* csiphy_set_power
* @power: Power state to be set.
*
* Returns 0 if successful, or -EBUSY if the retry count is exceeded.
*/
static int csiphy_set_power(struct isp_csiphy *phy, u32 power)
{
u32 reg;
u8 retry_count;
isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,
ISPCSI2_PHY_CFG_PWR_CMD_MASK, power);
retry_count = 0;
do {
udelay(50);
reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG) &
ISPCSI2_PHY_CFG_PWR_STATUS_MASK;
if (reg != power >> 2)
retry_count++;
} while ((reg != power >> 2) && (retry_count < 100));
if (retry_count == 100) {
printk(KERN_ERR "CSI2 CIO set power failed!\n");
return -EBUSY;
}
return 0;
}
/*
* csiphy_dphy_config - Configure CSI2 D-PHY parameters.
*
* Called with phy->mutex taken.
*/
static void csiphy_dphy_config(struct isp_csiphy *phy)
{
u32 reg;
/* Set up ISPCSIPHY_REG0 */
reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG0);
reg &= ~(ISPCSIPHY_REG0_THS_TERM_MASK |
ISPCSIPHY_REG0_THS_SETTLE_MASK);
reg |= phy->dphy.ths_term << ISPCSIPHY_REG0_THS_TERM_SHIFT;
reg |= phy->dphy.ths_settle << ISPCSIPHY_REG0_THS_SETTLE_SHIFT;
isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG0);
/* Set up ISPCSIPHY_REG1 */
reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG1);
reg &= ~(ISPCSIPHY_REG1_TCLK_TERM_MASK |
ISPCSIPHY_REG1_TCLK_MISS_MASK |
ISPCSIPHY_REG1_TCLK_SETTLE_MASK);
reg |= phy->dphy.tclk_term << ISPCSIPHY_REG1_TCLK_TERM_SHIFT;
reg |= phy->dphy.tclk_miss << ISPCSIPHY_REG1_TCLK_MISS_SHIFT;
reg |= phy->dphy.tclk_settle << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT;
isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG1);
}
static int csiphy_config(struct isp_csiphy *phy,
struct isp_csiphy_dphy_cfg *dphy,
struct isp_csiphy_lanes_cfg *lanes)
{
unsigned int used_lanes = 0;
unsigned int i;
/* Clock and data lanes verification */
for (i = 0; i < phy->num_data_lanes; i++) {
if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3)
return -EINVAL;
if (used_lanes & (1 << lanes->data[i].pos))
return -EINVAL;
used_lanes |= 1 << lanes->data[i].pos;
}
if (lanes->clk.pol > 1 || lanes->clk.pos > 3)
return -EINVAL;
if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))
return -EINVAL;
mutex_lock(&phy->mutex);
phy->dphy = *dphy;
phy->lanes = *lanes;
mutex_unlock(&phy->mutex);
return 0;
}
int omap3isp_csiphy_acquire(struct isp_csiphy *phy)
{
int rval;
if (phy->vdd == NULL) {
dev_err(phy->isp->dev, "Power regulator for CSI PHY not "
"available\n");
return -ENODEV;
}
mutex_lock(&phy->mutex);
rval = regulator_enable(phy->vdd);
if (rval < 0)
goto done;
rval = omap3isp_csi2_reset(phy->csi2);
if (rval < 0)
goto done;
csiphy_dphy_config(phy);
csiphy_lanes_config(phy);
rval = csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_ON);
if (rval) {
regulator_disable(phy->vdd);
goto done;
}
csiphy_power_autoswitch_enable(phy, true);
phy->phy_in_use = 1;
done:
mutex_unlock(&phy->mutex);
return rval;
}
void omap3isp_csiphy_release(struct isp_csiphy *phy)
{
mutex_lock(&phy->mutex);
if (phy->phy_in_use) {
csiphy_power_autoswitch_enable(phy, false);
csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_OFF);
regulator_disable(phy->vdd);
phy->phy_in_use = 0;
}
mutex_unlock(&phy->mutex);
}
/*
* omap3isp_csiphy_init - Initialize the CSI PHY frontends
*/
int omap3isp_csiphy_init(struct isp_device *isp)
{
struct isp_csiphy *phy1 = &isp->isp_csiphy1;
struct isp_csiphy *phy2 = &isp->isp_csiphy2;
isp->platform_cb.csiphy_config = csiphy_config;
phy2->isp = isp;
phy2->csi2 = &isp->isp_csi2a;
phy2->num_data_lanes = ISP_CSIPHY2_NUM_DATA_LANES;
phy2->cfg_regs = OMAP3_ISP_IOMEM_CSI2A_REGS1;
phy2->phy_regs = OMAP3_ISP_IOMEM_CSIPHY2;
mutex_init(&phy2->mutex);
if (isp->revision == ISP_REVISION_15_0) {
phy1->isp = isp;
phy1->csi2 = &isp->isp_csi2c;
phy1->num_data_lanes = ISP_CSIPHY1_NUM_DATA_LANES;
phy1->cfg_regs = OMAP3_ISP_IOMEM_CSI2C_REGS1;
phy1->phy_regs = OMAP3_ISP_IOMEM_CSIPHY1;
mutex_init(&phy1->mutex);
}
return 0;
}

63
drivers/media/platform/omap3isp/ispcsiphy.h Normal file
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@@ -0,0 +1,63 @@
/*
* ispcsiphy.h
*
* TI OMAP3 ISP - CSI PHY module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_CSI_PHY_H
#define OMAP3_ISP_CSI_PHY_H
#include <media/omap3isp.h>
struct isp_csi2_device;
struct regulator;
struct isp_csiphy_dphy_cfg {
u8 ths_term;
u8 ths_settle;
u8 tclk_term;
unsigned tclk_miss:1;
u8 tclk_settle;
};
struct isp_csiphy {
struct isp_device *isp;
struct mutex mutex; /* serialize csiphy configuration */
u8 phy_in_use;
struct isp_csi2_device *csi2;
struct regulator *vdd;
/* mem resources - enums as defined in enum isp_mem_resources */
unsigned int cfg_regs;
unsigned int phy_regs;
u8 num_data_lanes; /* number of CSI2 Data Lanes supported */
struct isp_csiphy_lanes_cfg lanes;
struct isp_csiphy_dphy_cfg dphy;
};
int omap3isp_csiphy_acquire(struct isp_csiphy *phy);
void omap3isp_csiphy_release(struct isp_csiphy *phy);
int omap3isp_csiphy_init(struct isp_device *isp);
#endif /* OMAP3_ISP_CSI_PHY_H */

117
drivers/media/platform/omap3isp/isph3a.h Normal file
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@@ -0,0 +1,117 @@
/*
* isph3a.h
*
* TI OMAP3 ISP - H3A AF module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: David Cohen <dacohen@gmail.com>
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_H3A_H
#define OMAP3_ISP_H3A_H
#include <linux/omap3isp.h>
/*
* ----------
* -H3A AEWB-
* ----------
*/
#define AEWB_PACKET_SIZE 16
#define AEWB_SATURATION_LIMIT 0x3ff
/* Flags for changed registers */
#define PCR_CHNG (1 << 0)
#define AEWWIN1_CHNG (1 << 1)
#define AEWINSTART_CHNG (1 << 2)
#define AEWINBLK_CHNG (1 << 3)
#define AEWSUBWIN_CHNG (1 << 4)
#define PRV_WBDGAIN_CHNG (1 << 5)
#define PRV_WBGAIN_CHNG (1 << 6)
/* ISPH3A REGISTERS bits */
#define ISPH3A_PCR_AF_EN (1 << 0)
#define ISPH3A_PCR_AF_ALAW_EN (1 << 1)
#define ISPH3A_PCR_AF_MED_EN (1 << 2)
#define ISPH3A_PCR_AF_BUSY (1 << 15)
#define ISPH3A_PCR_AEW_EN (1 << 16)
#define ISPH3A_PCR_AEW_ALAW_EN (1 << 17)
#define ISPH3A_PCR_AEW_BUSY (1 << 18)
#define ISPH3A_PCR_AEW_MASK (ISPH3A_PCR_AEW_ALAW_EN | \
ISPH3A_PCR_AEW_AVE2LMT_MASK)
/*
* --------
* -H3A AF-
* --------
*/
/* Peripheral Revision */
#define AFPID 0x0
#define AFCOEF_OFFSET 0x00000004 /* COEF base address */
/* PCR fields */
#define AF_BUSYAF (1 << 15)
#define AF_FVMODE (1 << 14)
#define AF_RGBPOS (0x7 << 11)
#define AF_MED_TH (0xFF << 3)
#define AF_MED_EN (1 << 2)
#define AF_ALAW_EN (1 << 1)
#define AF_EN (1 << 0)
#define AF_PCR_MASK (AF_FVMODE | AF_RGBPOS | AF_MED_TH | \
AF_MED_EN | AF_ALAW_EN)
/* AFPAX1 fields */
#define AF_PAXW (0x7F << 16)
#define AF_PAXH 0x7F
/* AFPAX2 fields */
#define AF_AFINCV (0xF << 13)
#define AF_PAXVC (0x7F << 6)
#define AF_PAXHC 0x3F
/* AFPAXSTART fields */
#define AF_PAXSH (0xFFF<<16)
#define AF_PAXSV 0xFFF
/* COEFFICIENT MASK */
#define AF_COEF_MASK0 0xFFF
#define AF_COEF_MASK1 (0xFFF<<16)
/* BIT SHIFTS */
#define AF_RGBPOS_SHIFT 11
#define AF_MED_TH_SHIFT 3
#define AF_PAXW_SHIFT 16
#define AF_LINE_INCR_SHIFT 13
#define AF_VT_COUNT_SHIFT 6
#define AF_HZ_START_SHIFT 16
#define AF_COEF_SHIFT 16
/* Init and cleanup functions */
int omap3isp_h3a_aewb_init(struct isp_device *isp);
int omap3isp_h3a_af_init(struct isp_device *isp);
void omap3isp_h3a_aewb_cleanup(struct isp_device *isp);
void omap3isp_h3a_af_cleanup(struct isp_device *isp);
#endif /* OMAP3_ISP_H3A_H */

368
drivers/media/platform/omap3isp/isph3a_aewb.c Normal file
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@@ -0,0 +1,368 @@
/*
* isph3a.c
*
* TI OMAP3 ISP - H3A module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: David Cohen <dacohen@gmail.com>
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#include <linux/slab.h>
#include <linux/uaccess.h>
#include "isp.h"
#include "isph3a.h"
#include "ispstat.h"
/*
* h3a_aewb_update_regs - Helper function to update h3a registers.
*/
static void h3a_aewb_setup_regs(struct ispstat *aewb, void *priv)
{
struct omap3isp_h3a_aewb_config *conf = priv;
u32 pcr;
u32 win1;
u32 start;
u32 blk;
u32 subwin;
if (aewb->state == ISPSTAT_DISABLED)
return;
isp_reg_writel(aewb->isp, aewb->active_buf->iommu_addr,
OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWBUFST);
if (!aewb->update)
return;
/* Converting config metadata into reg values */
pcr = conf->saturation_limit << ISPH3A_PCR_AEW_AVE2LMT_SHIFT;
pcr |= !!conf->alaw_enable << ISPH3A_PCR_AEW_ALAW_EN_SHIFT;
win1 = ((conf->win_height >> 1) - 1) << ISPH3A_AEWWIN1_WINH_SHIFT;
win1 |= ((conf->win_width >> 1) - 1) << ISPH3A_AEWWIN1_WINW_SHIFT;
win1 |= (conf->ver_win_count - 1) << ISPH3A_AEWWIN1_WINVC_SHIFT;
win1 |= (conf->hor_win_count - 1) << ISPH3A_AEWWIN1_WINHC_SHIFT;
start = conf->hor_win_start << ISPH3A_AEWINSTART_WINSH_SHIFT;
start |= conf->ver_win_start << ISPH3A_AEWINSTART_WINSV_SHIFT;
blk = conf->blk_ver_win_start << ISPH3A_AEWINBLK_WINSV_SHIFT;
blk |= ((conf->blk_win_height >> 1) - 1) << ISPH3A_AEWINBLK_WINH_SHIFT;
subwin = ((conf->subsample_ver_inc >> 1) - 1) <<
ISPH3A_AEWSUBWIN_AEWINCV_SHIFT;
subwin |= ((conf->subsample_hor_inc >> 1) - 1) <<
ISPH3A_AEWSUBWIN_AEWINCH_SHIFT;
isp_reg_writel(aewb->isp, win1, OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWWIN1);
isp_reg_writel(aewb->isp, start, OMAP3_ISP_IOMEM_H3A,
ISPH3A_AEWINSTART);
isp_reg_writel(aewb->isp, blk, OMAP3_ISP_IOMEM_H3A, ISPH3A_AEWINBLK);
isp_reg_writel(aewb->isp, subwin, OMAP3_ISP_IOMEM_H3A,
ISPH3A_AEWSUBWIN);
isp_reg_clr_set(aewb->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR,
ISPH3A_PCR_AEW_MASK, pcr);
aewb->update = 0;
aewb->config_counter += aewb->inc_config;
aewb->inc_config = 0;
aewb->buf_size = conf->buf_size;
}
static void h3a_aewb_enable(struct ispstat *aewb, int enable)
{
if (enable) {
isp_reg_set(aewb->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR,
ISPH3A_PCR_AEW_EN);
omap3isp_subclk_enable(aewb->isp, OMAP3_ISP_SUBCLK_AEWB);
} else {
isp_reg_clr(aewb->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR,
ISPH3A_PCR_AEW_EN);
omap3isp_subclk_disable(aewb->isp, OMAP3_ISP_SUBCLK_AEWB);
}
}
static int h3a_aewb_busy(struct ispstat *aewb)
{
return isp_reg_readl(aewb->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR)
& ISPH3A_PCR_BUSYAEAWB;
}
static u32 h3a_aewb_get_buf_size(struct omap3isp_h3a_aewb_config *conf)
{
/* Number of configured windows + extra row for black data */
u32 win_count = (conf->ver_win_count + 1) * conf->hor_win_count;
/*
* Unsaturated block counts for each 8 windows.
* 1 extra for the last (win_count % 8) windows if win_count is not
* divisible by 8.
*/
win_count += (win_count + 7) / 8;
return win_count * AEWB_PACKET_SIZE;
}
static int h3a_aewb_validate_params(struct ispstat *aewb, void *new_conf)
{
struct omap3isp_h3a_aewb_config *user_cfg = new_conf;
u32 buf_size;
if (unlikely(user_cfg->saturation_limit >
OMAP3ISP_AEWB_MAX_SATURATION_LIM))
return -EINVAL;
if (unlikely(user_cfg->win_height < OMAP3ISP_AEWB_MIN_WIN_H ||
user_cfg->win_height > OMAP3ISP_AEWB_MAX_WIN_H ||
user_cfg->win_height & 0x01))
return -EINVAL;
if (unlikely(user_cfg->win_width < OMAP3ISP_AEWB_MIN_WIN_W ||
user_cfg->win_width > OMAP3ISP_AEWB_MAX_WIN_W ||
user_cfg->win_width & 0x01))
return -EINVAL;
if (unlikely(user_cfg->ver_win_count < OMAP3ISP_AEWB_MIN_WINVC ||
user_cfg->ver_win_count > OMAP3ISP_AEWB_MAX_WINVC))
return -EINVAL;
if (unlikely(user_cfg->hor_win_count < OMAP3ISP_AEWB_MIN_WINHC ||
user_cfg->hor_win_count > OMAP3ISP_AEWB_MAX_WINHC))
return -EINVAL;
if (unlikely(user_cfg->ver_win_start > OMAP3ISP_AEWB_MAX_WINSTART))
return -EINVAL;
if (unlikely(user_cfg->hor_win_start > OMAP3ISP_AEWB_MAX_WINSTART))
return -EINVAL;
if (unlikely(user_cfg->blk_ver_win_start > OMAP3ISP_AEWB_MAX_WINSTART))
return -EINVAL;
if (unlikely(user_cfg->blk_win_height < OMAP3ISP_AEWB_MIN_WIN_H ||
user_cfg->blk_win_height > OMAP3ISP_AEWB_MAX_WIN_H ||
user_cfg->blk_win_height & 0x01))
return -EINVAL;
if (unlikely(user_cfg->subsample_ver_inc < OMAP3ISP_AEWB_MIN_SUB_INC ||
user_cfg->subsample_ver_inc > OMAP3ISP_AEWB_MAX_SUB_INC ||
user_cfg->subsample_ver_inc & 0x01))
return -EINVAL;
if (unlikely(user_cfg->subsample_hor_inc < OMAP3ISP_AEWB_MIN_SUB_INC ||
user_cfg->subsample_hor_inc > OMAP3ISP_AEWB_MAX_SUB_INC ||
user_cfg->subsample_hor_inc & 0x01))
return -EINVAL;
buf_size = h3a_aewb_get_buf_size(user_cfg);
if (buf_size > user_cfg->buf_size)
user_cfg->buf_size = buf_size;
else if (user_cfg->buf_size > OMAP3ISP_AEWB_MAX_BUF_SIZE)
user_cfg->buf_size = OMAP3ISP_AEWB_MAX_BUF_SIZE;
return 0;
}
/*
* h3a_aewb_set_params - Helper function to check & store user given params.
* @new_conf: Pointer to AE and AWB parameters struct.
*
* As most of them are busy-lock registers, need to wait until AEW_BUSY = 0 to
* program them during ISR.
*/
static void h3a_aewb_set_params(struct ispstat *aewb, void *new_conf)
{
struct omap3isp_h3a_aewb_config *user_cfg = new_conf;
struct omap3isp_h3a_aewb_config *cur_cfg = aewb->priv;
int update = 0;
if (cur_cfg->saturation_limit != user_cfg->saturation_limit) {
cur_cfg->saturation_limit = user_cfg->saturation_limit;
update = 1;
}
if (cur_cfg->alaw_enable != user_cfg->alaw_enable) {
cur_cfg->alaw_enable = user_cfg->alaw_enable;
update = 1;
}
if (cur_cfg->win_height != user_cfg->win_height) {
cur_cfg->win_height = user_cfg->win_height;
update = 1;
}
if (cur_cfg->win_width != user_cfg->win_width) {
cur_cfg->win_width = user_cfg->win_width;
update = 1;
}
if (cur_cfg->ver_win_count != user_cfg->ver_win_count) {
cur_cfg->ver_win_count = user_cfg->ver_win_count;
update = 1;
}
if (cur_cfg->hor_win_count != user_cfg->hor_win_count) {
cur_cfg->hor_win_count = user_cfg->hor_win_count;
update = 1;
}
if (cur_cfg->ver_win_start != user_cfg->ver_win_start) {
cur_cfg->ver_win_start = user_cfg->ver_win_start;
update = 1;
}
if (cur_cfg->hor_win_start != user_cfg->hor_win_start) {
cur_cfg->hor_win_start = user_cfg->hor_win_start;
update = 1;
}
if (cur_cfg->blk_ver_win_start != user_cfg->blk_ver_win_start) {
cur_cfg->blk_ver_win_start = user_cfg->blk_ver_win_start;
update = 1;
}
if (cur_cfg->blk_win_height != user_cfg->blk_win_height) {
cur_cfg->blk_win_height = user_cfg->blk_win_height;
update = 1;
}
if (cur_cfg->subsample_ver_inc != user_cfg->subsample_ver_inc) {
cur_cfg->subsample_ver_inc = user_cfg->subsample_ver_inc;
update = 1;
}
if (cur_cfg->subsample_hor_inc != user_cfg->subsample_hor_inc) {
cur_cfg->subsample_hor_inc = user_cfg->subsample_hor_inc;
update = 1;
}
if (update || !aewb->configured) {
aewb->inc_config++;
aewb->update = 1;
cur_cfg->buf_size = h3a_aewb_get_buf_size(cur_cfg);
}
}
static long h3a_aewb_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct ispstat *stat = v4l2_get_subdevdata(sd);
switch (cmd) {
case VIDIOC_OMAP3ISP_AEWB_CFG:
return omap3isp_stat_config(stat, arg);
case VIDIOC_OMAP3ISP_STAT_REQ:
return omap3isp_stat_request_statistics(stat, arg);
case VIDIOC_OMAP3ISP_STAT_EN: {
unsigned long *en = arg;
return omap3isp_stat_enable(stat, !!*en);
}
}
return -ENOIOCTLCMD;
}
static const struct ispstat_ops h3a_aewb_ops = {
.validate_params = h3a_aewb_validate_params,
.set_params = h3a_aewb_set_params,
.setup_regs = h3a_aewb_setup_regs,
.enable = h3a_aewb_enable,
.busy = h3a_aewb_busy,
};
static const struct v4l2_subdev_core_ops h3a_aewb_subdev_core_ops = {
.ioctl = h3a_aewb_ioctl,
.subscribe_event = omap3isp_stat_subscribe_event,
.unsubscribe_event = omap3isp_stat_unsubscribe_event,
};
static const struct v4l2_subdev_video_ops h3a_aewb_subdev_video_ops = {
.s_stream = omap3isp_stat_s_stream,
};
static const struct v4l2_subdev_ops h3a_aewb_subdev_ops = {
.core = &h3a_aewb_subdev_core_ops,
.video = &h3a_aewb_subdev_video_ops,
};
/*
* omap3isp_h3a_aewb_init - Module Initialisation.
*/
int omap3isp_h3a_aewb_init(struct isp_device *isp)
{
struct ispstat *aewb = &isp->isp_aewb;
struct omap3isp_h3a_aewb_config *aewb_cfg;
struct omap3isp_h3a_aewb_config *aewb_recover_cfg;
int ret;
aewb_cfg = kzalloc(sizeof(*aewb_cfg), GFP_KERNEL);
if (!aewb_cfg)
return -ENOMEM;
memset(aewb, 0, sizeof(*aewb));
aewb->ops = &h3a_aewb_ops;
aewb->priv = aewb_cfg;
aewb->dma_ch = -1;
aewb->event_type = V4L2_EVENT_OMAP3ISP_AEWB;
aewb->isp = isp;
/* Set recover state configuration */
aewb_recover_cfg = kzalloc(sizeof(*aewb_recover_cfg), GFP_KERNEL);
if (!aewb_recover_cfg) {
dev_err(aewb->isp->dev, "AEWB: cannot allocate memory for "
"recover configuration.\n");
ret = -ENOMEM;
goto err_recover_alloc;
}
aewb_recover_cfg->saturation_limit = OMAP3ISP_AEWB_MAX_SATURATION_LIM;
aewb_recover_cfg->win_height = OMAP3ISP_AEWB_MIN_WIN_H;
aewb_recover_cfg->win_width = OMAP3ISP_AEWB_MIN_WIN_W;
aewb_recover_cfg->ver_win_count = OMAP3ISP_AEWB_MIN_WINVC;
aewb_recover_cfg->hor_win_count = OMAP3ISP_AEWB_MIN_WINHC;
aewb_recover_cfg->blk_ver_win_start = aewb_recover_cfg->ver_win_start +
aewb_recover_cfg->win_height * aewb_recover_cfg->ver_win_count;
aewb_recover_cfg->blk_win_height = OMAP3ISP_AEWB_MIN_WIN_H;
aewb_recover_cfg->subsample_ver_inc = OMAP3ISP_AEWB_MIN_SUB_INC;
aewb_recover_cfg->subsample_hor_inc = OMAP3ISP_AEWB_MIN_SUB_INC;
if (h3a_aewb_validate_params(aewb, aewb_recover_cfg)) {
dev_err(aewb->isp->dev, "AEWB: recover configuration is "
"invalid.\n");
ret = -EINVAL;
goto err_conf;
}
aewb_recover_cfg->buf_size = h3a_aewb_get_buf_size(aewb_recover_cfg);
aewb->recover_priv = aewb_recover_cfg;
ret = omap3isp_stat_init(aewb, "AEWB", &h3a_aewb_subdev_ops);
if (ret)
goto err_conf;
return 0;
err_conf:
kfree(aewb_recover_cfg);
err_recover_alloc:
kfree(aewb_cfg);
return ret;
}
/*
* omap3isp_h3a_aewb_cleanup - Module exit.
*/
void omap3isp_h3a_aewb_cleanup(struct isp_device *isp)
{
kfree(isp->isp_aewb.priv);
kfree(isp->isp_aewb.recover_priv);
omap3isp_stat_cleanup(&isp->isp_aewb);
}

423
drivers/media/platform/omap3isp/isph3a_af.c Normal file
View File

@@ -0,0 +1,423 @@
/*
* isph3a_af.c
*
* TI OMAP3 ISP - H3A AF module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: David Cohen <dacohen@gmail.com>
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
/* Linux specific include files */
#include <linux/device.h>
#include <linux/slab.h>
#include "isp.h"
#include "isph3a.h"
#include "ispstat.h"
#define IS_OUT_OF_BOUNDS(value, min, max) \
(((value) < (min)) || ((value) > (max)))
static void h3a_af_setup_regs(struct ispstat *af, void *priv)
{
struct omap3isp_h3a_af_config *conf = priv;
u32 pcr;
u32 pax1;
u32 pax2;
u32 paxstart;
u32 coef;
u32 base_coef_set0;
u32 base_coef_set1;
int index;
if (af->state == ISPSTAT_DISABLED)
return;
isp_reg_writel(af->isp, af->active_buf->iommu_addr, OMAP3_ISP_IOMEM_H3A,
ISPH3A_AFBUFST);
if (!af->update)
return;
/* Configure Hardware Registers */
pax1 = ((conf->paxel.width >> 1) - 1) << AF_PAXW_SHIFT;
/* Set height in AFPAX1 */
pax1 |= (conf->paxel.height >> 1) - 1;
isp_reg_writel(af->isp, pax1, OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAX1);
/* Configure AFPAX2 Register */
/* Set Line Increment in AFPAX2 Register */
pax2 = ((conf->paxel.line_inc >> 1) - 1) << AF_LINE_INCR_SHIFT;
/* Set Vertical Count */
pax2 |= (conf->paxel.v_cnt - 1) << AF_VT_COUNT_SHIFT;
/* Set Horizontal Count */
pax2 |= (conf->paxel.h_cnt - 1);
isp_reg_writel(af->isp, pax2, OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAX2);
/* Configure PAXSTART Register */
/*Configure Horizontal Start */
paxstart = conf->paxel.h_start << AF_HZ_START_SHIFT;
/* Configure Vertical Start */
paxstart |= conf->paxel.v_start;
isp_reg_writel(af->isp, paxstart, OMAP3_ISP_IOMEM_H3A,
ISPH3A_AFPAXSTART);
/*SetIIRSH Register */
isp_reg_writel(af->isp, conf->iir.h_start,
OMAP3_ISP_IOMEM_H3A, ISPH3A_AFIIRSH);
base_coef_set0 = ISPH3A_AFCOEF010;
base_coef_set1 = ISPH3A_AFCOEF110;
for (index = 0; index <= 8; index += 2) {
/*Set IIR Filter0 Coefficients */
coef = 0;
coef |= conf->iir.coeff_set0[index];
coef |= conf->iir.coeff_set0[index + 1] <<
AF_COEF_SHIFT;
isp_reg_writel(af->isp, coef, OMAP3_ISP_IOMEM_H3A,
base_coef_set0);
base_coef_set0 += AFCOEF_OFFSET;
/*Set IIR Filter1 Coefficients */
coef = 0;
coef |= conf->iir.coeff_set1[index];
coef |= conf->iir.coeff_set1[index + 1] <<
AF_COEF_SHIFT;
isp_reg_writel(af->isp, coef, OMAP3_ISP_IOMEM_H3A,
base_coef_set1);
base_coef_set1 += AFCOEF_OFFSET;
}
/* set AFCOEF0010 Register */
isp_reg_writel(af->isp, conf->iir.coeff_set0[10],
OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF0010);
/* set AFCOEF1010 Register */
isp_reg_writel(af->isp, conf->iir.coeff_set1[10],
OMAP3_ISP_IOMEM_H3A, ISPH3A_AFCOEF1010);
/* PCR Register */
/* Set RGB Position */
pcr = conf->rgb_pos << AF_RGBPOS_SHIFT;
/* Set Accumulator Mode */
if (conf->fvmode == OMAP3ISP_AF_MODE_PEAK)
pcr |= AF_FVMODE;
/* Set A-law */
if (conf->alaw_enable)
pcr |= AF_ALAW_EN;
/* HMF Configurations */
if (conf->hmf.enable) {
/* Enable HMF */
pcr |= AF_MED_EN;
/* Set Median Threshold */
pcr |= conf->hmf.threshold << AF_MED_TH_SHIFT;
}
/* Set PCR Register */
isp_reg_clr_set(af->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR,
AF_PCR_MASK, pcr);
af->update = 0;
af->config_counter += af->inc_config;
af->inc_config = 0;
af->buf_size = conf->buf_size;
}
static void h3a_af_enable(struct ispstat *af, int enable)
{
if (enable) {
isp_reg_set(af->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR,
ISPH3A_PCR_AF_EN);
omap3isp_subclk_enable(af->isp, OMAP3_ISP_SUBCLK_AF);
} else {
isp_reg_clr(af->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR,
ISPH3A_PCR_AF_EN);
omap3isp_subclk_disable(af->isp, OMAP3_ISP_SUBCLK_AF);
}
}
static int h3a_af_busy(struct ispstat *af)
{
return isp_reg_readl(af->isp, OMAP3_ISP_IOMEM_H3A, ISPH3A_PCR)
& ISPH3A_PCR_BUSYAF;
}
static u32 h3a_af_get_buf_size(struct omap3isp_h3a_af_config *conf)
{
return conf->paxel.h_cnt * conf->paxel.v_cnt * OMAP3ISP_AF_PAXEL_SIZE;
}
/* Function to check paxel parameters */
static int h3a_af_validate_params(struct ispstat *af, void *new_conf)
{
struct omap3isp_h3a_af_config *user_cfg = new_conf;
struct omap3isp_h3a_af_paxel *paxel_cfg = &user_cfg->paxel;
struct omap3isp_h3a_af_iir *iir_cfg = &user_cfg->iir;
int index;
u32 buf_size;
/* Check horizontal Count */
if (IS_OUT_OF_BOUNDS(paxel_cfg->h_cnt,
OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN,
OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MAX))
return -EINVAL;
/* Check Vertical Count */
if (IS_OUT_OF_BOUNDS(paxel_cfg->v_cnt,
OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN,
OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MAX))
return -EINVAL;
if (IS_OUT_OF_BOUNDS(paxel_cfg->height, OMAP3ISP_AF_PAXEL_HEIGHT_MIN,
OMAP3ISP_AF_PAXEL_HEIGHT_MAX) ||
paxel_cfg->height % 2)
return -EINVAL;
/* Check width */
if (IS_OUT_OF_BOUNDS(paxel_cfg->width, OMAP3ISP_AF_PAXEL_WIDTH_MIN,
OMAP3ISP_AF_PAXEL_WIDTH_MAX) ||
paxel_cfg->width % 2)
return -EINVAL;
/* Check Line Increment */
if (IS_OUT_OF_BOUNDS(paxel_cfg->line_inc,
OMAP3ISP_AF_PAXEL_INCREMENT_MIN,
OMAP3ISP_AF_PAXEL_INCREMENT_MAX) ||
paxel_cfg->line_inc % 2)
return -EINVAL;
/* Check Horizontal Start */
if ((paxel_cfg->h_start < iir_cfg->h_start) ||
IS_OUT_OF_BOUNDS(paxel_cfg->h_start,
OMAP3ISP_AF_PAXEL_HZSTART_MIN,
OMAP3ISP_AF_PAXEL_HZSTART_MAX))
return -EINVAL;
/* Check IIR */
for (index = 0; index < OMAP3ISP_AF_NUM_COEF; index++) {
if ((iir_cfg->coeff_set0[index]) > OMAP3ISP_AF_COEF_MAX)
return -EINVAL;
if ((iir_cfg->coeff_set1[index]) > OMAP3ISP_AF_COEF_MAX)
return -EINVAL;
}
if (IS_OUT_OF_BOUNDS(iir_cfg->h_start, OMAP3ISP_AF_IIRSH_MIN,
OMAP3ISP_AF_IIRSH_MAX))
return -EINVAL;
/* Hack: If paxel size is 12, the 10th AF window may be corrupted */
if ((paxel_cfg->h_cnt * paxel_cfg->v_cnt > 9) &&
(paxel_cfg->width * paxel_cfg->height == 12))
return -EINVAL;
buf_size = h3a_af_get_buf_size(user_cfg);
if (buf_size > user_cfg->buf_size)
/* User buf_size request wasn't enough */
user_cfg->buf_size = buf_size;
else if (user_cfg->buf_size > OMAP3ISP_AF_MAX_BUF_SIZE)
user_cfg->buf_size = OMAP3ISP_AF_MAX_BUF_SIZE;
return 0;
}
/* Update local parameters */
static void h3a_af_set_params(struct ispstat *af, void *new_conf)
{
struct omap3isp_h3a_af_config *user_cfg = new_conf;
struct omap3isp_h3a_af_config *cur_cfg = af->priv;
int update = 0;
int index;
/* alaw */
if (cur_cfg->alaw_enable != user_cfg->alaw_enable) {
update = 1;
goto out;
}
/* hmf */
if (cur_cfg->hmf.enable != user_cfg->hmf.enable) {
update = 1;
goto out;
}
if (cur_cfg->hmf.threshold != user_cfg->hmf.threshold) {
update = 1;
goto out;
}
/* rgbpos */
if (cur_cfg->rgb_pos != user_cfg->rgb_pos) {
update = 1;
goto out;
}
/* iir */
if (cur_cfg->iir.h_start != user_cfg->iir.h_start) {
update = 1;
goto out;
}
for (index = 0; index < OMAP3ISP_AF_NUM_COEF; index++) {
if (cur_cfg->iir.coeff_set0[index] !=
user_cfg->iir.coeff_set0[index]) {
update = 1;
goto out;
}
if (cur_cfg->iir.coeff_set1[index] !=
user_cfg->iir.coeff_set1[index]) {
update = 1;
goto out;
}
}
/* paxel */
if ((cur_cfg->paxel.width != user_cfg->paxel.width) ||
(cur_cfg->paxel.height != user_cfg->paxel.height) ||
(cur_cfg->paxel.h_start != user_cfg->paxel.h_start) ||
(cur_cfg->paxel.v_start != user_cfg->paxel.v_start) ||
(cur_cfg->paxel.h_cnt != user_cfg->paxel.h_cnt) ||
(cur_cfg->paxel.v_cnt != user_cfg->paxel.v_cnt) ||
(cur_cfg->paxel.line_inc != user_cfg->paxel.line_inc)) {
update = 1;
goto out;
}
/* af_mode */
if (cur_cfg->fvmode != user_cfg->fvmode)
update = 1;
out:
if (update || !af->configured) {
memcpy(cur_cfg, user_cfg, sizeof(*cur_cfg));
af->inc_config++;
af->update = 1;
/*
* User might be asked for a bigger buffer than necessary for
* this configuration. In order to return the right amount of
* data during buffer request, let's calculate the size here
* instead of stick with user_cfg->buf_size.
*/
cur_cfg->buf_size = h3a_af_get_buf_size(cur_cfg);
}
}
static long h3a_af_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct ispstat *stat = v4l2_get_subdevdata(sd);
switch (cmd) {
case VIDIOC_OMAP3ISP_AF_CFG:
return omap3isp_stat_config(stat, arg);
case VIDIOC_OMAP3ISP_STAT_REQ:
return omap3isp_stat_request_statistics(stat, arg);
case VIDIOC_OMAP3ISP_STAT_EN: {
int *en = arg;
return omap3isp_stat_enable(stat, !!*en);
}
}
return -ENOIOCTLCMD;
}
static const struct ispstat_ops h3a_af_ops = {
.validate_params = h3a_af_validate_params,
.set_params = h3a_af_set_params,
.setup_regs = h3a_af_setup_regs,
.enable = h3a_af_enable,
.busy = h3a_af_busy,
};
static const struct v4l2_subdev_core_ops h3a_af_subdev_core_ops = {
.ioctl = h3a_af_ioctl,
.subscribe_event = omap3isp_stat_subscribe_event,
.unsubscribe_event = omap3isp_stat_unsubscribe_event,
};
static const struct v4l2_subdev_video_ops h3a_af_subdev_video_ops = {
.s_stream = omap3isp_stat_s_stream,
};
static const struct v4l2_subdev_ops h3a_af_subdev_ops = {
.core = &h3a_af_subdev_core_ops,
.video = &h3a_af_subdev_video_ops,
};
/* Function to register the AF character device driver. */
int omap3isp_h3a_af_init(struct isp_device *isp)
{
struct ispstat *af = &isp->isp_af;
struct omap3isp_h3a_af_config *af_cfg;
struct omap3isp_h3a_af_config *af_recover_cfg;
int ret;
af_cfg = kzalloc(sizeof(*af_cfg), GFP_KERNEL);
if (af_cfg == NULL)
return -ENOMEM;
memset(af, 0, sizeof(*af));
af->ops = &h3a_af_ops;
af->priv = af_cfg;
af->dma_ch = -1;
af->event_type = V4L2_EVENT_OMAP3ISP_AF;
af->isp = isp;
/* Set recover state configuration */
af_recover_cfg = kzalloc(sizeof(*af_recover_cfg), GFP_KERNEL);
if (!af_recover_cfg) {
dev_err(af->isp->dev, "AF: cannot allocate memory for recover "
"configuration.\n");
ret = -ENOMEM;
goto err_recover_alloc;
}
af_recover_cfg->paxel.h_start = OMAP3ISP_AF_PAXEL_HZSTART_MIN;
af_recover_cfg->paxel.width = OMAP3ISP_AF_PAXEL_WIDTH_MIN;
af_recover_cfg->paxel.height = OMAP3ISP_AF_PAXEL_HEIGHT_MIN;
af_recover_cfg->paxel.h_cnt = OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN;
af_recover_cfg->paxel.v_cnt = OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN;
af_recover_cfg->paxel.line_inc = OMAP3ISP_AF_PAXEL_INCREMENT_MIN;
if (h3a_af_validate_params(af, af_recover_cfg)) {
dev_err(af->isp->dev, "AF: recover configuration is "
"invalid.\n");
ret = -EINVAL;
goto err_conf;
}
af_recover_cfg->buf_size = h3a_af_get_buf_size(af_recover_cfg);
af->recover_priv = af_recover_cfg;
ret = omap3isp_stat_init(af, "AF", &h3a_af_subdev_ops);
if (ret)
goto err_conf;
return 0;
err_conf:
kfree(af_recover_cfg);
err_recover_alloc:
kfree(af_cfg);
return ret;
}
void omap3isp_h3a_af_cleanup(struct isp_device *isp)
{
kfree(isp->isp_af.priv);
kfree(isp->isp_af.recover_priv);
omap3isp_stat_cleanup(&isp->isp_af);
}

518
drivers/media/platform/omap3isp/isphist.c Normal file
View File

@@ -0,0 +1,518 @@
/*
* isphist.c
*
* TI OMAP3 ISP - Histogram module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: David Cohen <dacohen@gmail.com>
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/device.h>
#include "isp.h"
#include "ispreg.h"
#include "isphist.h"
#define HIST_CONFIG_DMA 1
#define HIST_USING_DMA(hist) ((hist)->dma_ch >= 0)
/*
* hist_reset_mem - clear Histogram memory before start stats engine.
*/
static void hist_reset_mem(struct ispstat *hist)
{
struct isp_device *isp = hist->isp;
struct omap3isp_hist_config *conf = hist->priv;
unsigned int i;
isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
/*
* By setting it, the histogram internal buffer is being cleared at the
* same time it's being read. This bit must be cleared afterwards.
*/
isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
/*
* We'll clear 4 words at each iteration for optimization. It avoids
* 3/4 of the jumps. We also know HIST_MEM_SIZE is divisible by 4.
*/
for (i = OMAP3ISP_HIST_MEM_SIZE / 4; i > 0; i--) {
isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
}
isp_reg_clr(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
hist->wait_acc_frames = conf->num_acc_frames;
}
static void hist_dma_config(struct ispstat *hist)
{
hist->dma_config.data_type = OMAP_DMA_DATA_TYPE_S32;
hist->dma_config.sync_mode = OMAP_DMA_SYNC_ELEMENT;
hist->dma_config.frame_count = 1;
hist->dma_config.src_amode = OMAP_DMA_AMODE_CONSTANT;
hist->dma_config.src_start = OMAP3ISP_HIST_REG_BASE + ISPHIST_DATA;
hist->dma_config.dst_amode = OMAP_DMA_AMODE_POST_INC;
hist->dma_config.src_or_dst_synch = OMAP_DMA_SRC_SYNC;
}
/*
* hist_setup_regs - Helper function to update Histogram registers.
*/
static void hist_setup_regs(struct ispstat *hist, void *priv)
{
struct isp_device *isp = hist->isp;
struct omap3isp_hist_config *conf = priv;
int c;
u32 cnt;
u32 wb_gain;
u32 reg_hor[OMAP3ISP_HIST_MAX_REGIONS];
u32 reg_ver[OMAP3ISP_HIST_MAX_REGIONS];
if (!hist->update || hist->state == ISPSTAT_DISABLED ||
hist->state == ISPSTAT_DISABLING)
return;
cnt = conf->cfa << ISPHIST_CNT_CFA_SHIFT;
wb_gain = conf->wg[0] << ISPHIST_WB_GAIN_WG00_SHIFT;
wb_gain |= conf->wg[1] << ISPHIST_WB_GAIN_WG01_SHIFT;
wb_gain |= conf->wg[2] << ISPHIST_WB_GAIN_WG02_SHIFT;
if (conf->cfa == OMAP3ISP_HIST_CFA_BAYER)
wb_gain |= conf->wg[3] << ISPHIST_WB_GAIN_WG03_SHIFT;
/* Regions size and position */
for (c = 0; c < OMAP3ISP_HIST_MAX_REGIONS; c++) {
if (c < conf->num_regions) {
reg_hor[c] = conf->region[c].h_start <<
ISPHIST_REG_START_SHIFT;
reg_hor[c] = conf->region[c].h_end <<
ISPHIST_REG_END_SHIFT;
reg_ver[c] = conf->region[c].v_start <<
ISPHIST_REG_START_SHIFT;
reg_ver[c] = conf->region[c].v_end <<
ISPHIST_REG_END_SHIFT;
} else {
reg_hor[c] = 0;
reg_ver[c] = 0;
}
}
cnt |= conf->hist_bins << ISPHIST_CNT_BINS_SHIFT;
switch (conf->hist_bins) {
case OMAP3ISP_HIST_BINS_256:
cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 8) <<
ISPHIST_CNT_SHIFT_SHIFT;
break;
case OMAP3ISP_HIST_BINS_128:
cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 7) <<
ISPHIST_CNT_SHIFT_SHIFT;
break;
case OMAP3ISP_HIST_BINS_64:
cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 6) <<
ISPHIST_CNT_SHIFT_SHIFT;
break;
default: /* OMAP3ISP_HIST_BINS_32 */
cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 5) <<
ISPHIST_CNT_SHIFT_SHIFT;
break;
}
hist_reset_mem(hist);
isp_reg_writel(isp, cnt, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT);
isp_reg_writel(isp, wb_gain, OMAP3_ISP_IOMEM_HIST, ISPHIST_WB_GAIN);
isp_reg_writel(isp, reg_hor[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_HORZ);
isp_reg_writel(isp, reg_ver[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_VERT);
isp_reg_writel(isp, reg_hor[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_HORZ);
isp_reg_writel(isp, reg_ver[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_VERT);
isp_reg_writel(isp, reg_hor[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_HORZ);
isp_reg_writel(isp, reg_ver[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_VERT);
isp_reg_writel(isp, reg_hor[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_HORZ);
isp_reg_writel(isp, reg_ver[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_VERT);
hist->update = 0;
hist->config_counter += hist->inc_config;
hist->inc_config = 0;
hist->buf_size = conf->buf_size;
}
static void hist_enable(struct ispstat *hist, int enable)
{
if (enable) {
isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
ISPHIST_PCR_ENABLE);
omap3isp_subclk_enable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
} else {
isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
ISPHIST_PCR_ENABLE);
omap3isp_subclk_disable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
}
}
static int hist_busy(struct ispstat *hist)
{
return isp_reg_readl(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR)
& ISPHIST_PCR_BUSY;
}
static void hist_dma_cb(int lch, u16 ch_status, void *data)
{
struct ispstat *hist = data;
if (ch_status & ~OMAP_DMA_BLOCK_IRQ) {
dev_dbg(hist->isp->dev, "hist: DMA error. status = 0x%04x\n",
ch_status);
omap_stop_dma(lch);
hist_reset_mem(hist);
atomic_set(&hist->buf_err, 1);
}
isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
ISPHIST_CNT_CLEAR);
omap3isp_stat_dma_isr(hist);
if (hist->state != ISPSTAT_DISABLED)
omap3isp_hist_dma_done(hist->isp);
}
static int hist_buf_dma(struct ispstat *hist)
{
dma_addr_t dma_addr = hist->active_buf->dma_addr;
if (unlikely(!dma_addr)) {
dev_dbg(hist->isp->dev, "hist: invalid DMA buffer address\n");
hist_reset_mem(hist);
return STAT_NO_BUF;
}
isp_reg_writel(hist->isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
ISPHIST_CNT_CLEAR);
omap3isp_flush(hist->isp);
hist->dma_config.dst_start = dma_addr;
hist->dma_config.elem_count = hist->buf_size / sizeof(u32);
omap_set_dma_params(hist->dma_ch, &hist->dma_config);
omap_start_dma(hist->dma_ch);
return STAT_BUF_WAITING_DMA;
}
static int hist_buf_pio(struct ispstat *hist)
{
struct isp_device *isp = hist->isp;
u32 *buf = hist->active_buf->virt_addr;
unsigned int i;
if (!buf) {
dev_dbg(isp->dev, "hist: invalid PIO buffer address\n");
hist_reset_mem(hist);
return STAT_NO_BUF;
}
isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
/*
* By setting it, the histogram internal buffer is being cleared at the
* same time it's being read. This bit must be cleared just after all
* data is acquired.
*/
isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
/*
* We'll read 4 times a 4-bytes-word at each iteration for
* optimization. It avoids 3/4 of the jumps. We also know buf_size is
* divisible by 16.
*/
for (i = hist->buf_size / 16; i > 0; i--) {
*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
*buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
}
isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
ISPHIST_CNT_CLEAR);
return STAT_BUF_DONE;
}
/*
* hist_buf_process - Callback from ISP driver for HIST interrupt.
*/
static int hist_buf_process(struct ispstat *hist)
{
struct omap3isp_hist_config *user_cfg = hist->priv;
int ret;
if (atomic_read(&hist->buf_err) || hist->state != ISPSTAT_ENABLED) {
hist_reset_mem(hist);
return STAT_NO_BUF;
}
if (--(hist->wait_acc_frames))
return STAT_NO_BUF;
if (HIST_USING_DMA(hist))
ret = hist_buf_dma(hist);
else
ret = hist_buf_pio(hist);
hist->wait_acc_frames = user_cfg->num_acc_frames;
return ret;
}
static u32 hist_get_buf_size(struct omap3isp_hist_config *conf)
{
return OMAP3ISP_HIST_MEM_SIZE_BINS(conf->hist_bins) * conf->num_regions;
}
/*
* hist_validate_params - Helper function to check user given params.
* @user_cfg: Pointer to user configuration structure.
*
* Returns 0 on success configuration.
*/
static int hist_validate_params(struct ispstat *hist, void *new_conf)
{
struct omap3isp_hist_config *user_cfg = new_conf;
int c;
u32 buf_size;
if (user_cfg->cfa > OMAP3ISP_HIST_CFA_FOVEONX3)
return -EINVAL;
/* Regions size and position */
if ((user_cfg->num_regions < OMAP3ISP_HIST_MIN_REGIONS) ||
(user_cfg->num_regions > OMAP3ISP_HIST_MAX_REGIONS))
return -EINVAL;
/* Regions */
for (c = 0; c < user_cfg->num_regions; c++) {
if (user_cfg->region[c].h_start & ~ISPHIST_REG_START_END_MASK)
return -EINVAL;
if (user_cfg->region[c].h_end & ~ISPHIST_REG_START_END_MASK)
return -EINVAL;
if (user_cfg->region[c].v_start & ~ISPHIST_REG_START_END_MASK)
return -EINVAL;
if (user_cfg->region[c].v_end & ~ISPHIST_REG_START_END_MASK)
return -EINVAL;
if (user_cfg->region[c].h_start > user_cfg->region[c].h_end)
return -EINVAL;
if (user_cfg->region[c].v_start > user_cfg->region[c].v_end)
return -EINVAL;
}
switch (user_cfg->num_regions) {
case 1:
if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_256)
return -EINVAL;
break;
case 2:
if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_128)
return -EINVAL;
break;
default: /* 3 or 4 */
if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_64)
return -EINVAL;
break;
}
buf_size = hist_get_buf_size(user_cfg);
if (buf_size > user_cfg->buf_size)
/* User's buf_size request wasn't enoght */
user_cfg->buf_size = buf_size;
else if (user_cfg->buf_size > OMAP3ISP_HIST_MAX_BUF_SIZE)
user_cfg->buf_size = OMAP3ISP_HIST_MAX_BUF_SIZE;
return 0;
}
static int hist_comp_params(struct ispstat *hist,
struct omap3isp_hist_config *user_cfg)
{
struct omap3isp_hist_config *cur_cfg = hist->priv;
int c;
if (cur_cfg->cfa != user_cfg->cfa)
return 1;
if (cur_cfg->num_acc_frames != user_cfg->num_acc_frames)
return 1;
if (cur_cfg->hist_bins != user_cfg->hist_bins)
return 1;
for (c = 0; c < OMAP3ISP_HIST_MAX_WG; c++) {
if (c == 3 && user_cfg->cfa == OMAP3ISP_HIST_CFA_FOVEONX3)
break;
else if (cur_cfg->wg[c] != user_cfg->wg[c])
return 1;
}
if (cur_cfg->num_regions != user_cfg->num_regions)
return 1;
/* Regions */
for (c = 0; c < user_cfg->num_regions; c++) {
if (cur_cfg->region[c].h_start != user_cfg->region[c].h_start)
return 1;
if (cur_cfg->region[c].h_end != user_cfg->region[c].h_end)
return 1;
if (cur_cfg->region[c].v_start != user_cfg->region[c].v_start)
return 1;
if (cur_cfg->region[c].v_end != user_cfg->region[c].v_end)
return 1;
}
return 0;
}
/*
* hist_update_params - Helper function to check and store user given params.
* @new_conf: Pointer to user configuration structure.
*/
static void hist_set_params(struct ispstat *hist, void *new_conf)
{
struct omap3isp_hist_config *user_cfg = new_conf;
struct omap3isp_hist_config *cur_cfg = hist->priv;
if (!hist->configured || hist_comp_params(hist, user_cfg)) {
memcpy(cur_cfg, user_cfg, sizeof(*user_cfg));
if (user_cfg->num_acc_frames == 0)
user_cfg->num_acc_frames = 1;
hist->inc_config++;
hist->update = 1;
/*
* User might be asked for a bigger buffer than necessary for
* this configuration. In order to return the right amount of
* data during buffer request, let's calculate the size here
* instead of stick with user_cfg->buf_size.
*/
cur_cfg->buf_size = hist_get_buf_size(cur_cfg);
}
}
static long hist_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct ispstat *stat = v4l2_get_subdevdata(sd);
switch (cmd) {
case VIDIOC_OMAP3ISP_HIST_CFG:
return omap3isp_stat_config(stat, arg);
case VIDIOC_OMAP3ISP_STAT_REQ:
return omap3isp_stat_request_statistics(stat, arg);
case VIDIOC_OMAP3ISP_STAT_EN: {
int *en = arg;
return omap3isp_stat_enable(stat, !!*en);
}
}
return -ENOIOCTLCMD;
}
static const struct ispstat_ops hist_ops = {
.validate_params = hist_validate_params,
.set_params = hist_set_params,
.setup_regs = hist_setup_regs,
.enable = hist_enable,
.busy = hist_busy,
.buf_process = hist_buf_process,
};
static const struct v4l2_subdev_core_ops hist_subdev_core_ops = {
.ioctl = hist_ioctl,
.subscribe_event = omap3isp_stat_subscribe_event,
.unsubscribe_event = omap3isp_stat_unsubscribe_event,
};
static const struct v4l2_subdev_video_ops hist_subdev_video_ops = {
.s_stream = omap3isp_stat_s_stream,
};
static const struct v4l2_subdev_ops hist_subdev_ops = {
.core = &hist_subdev_core_ops,
.video = &hist_subdev_video_ops,
};
/*
* omap3isp_hist_init - Module Initialization.
*/
int omap3isp_hist_init(struct isp_device *isp)
{
struct ispstat *hist = &isp->isp_hist;
struct omap3isp_hist_config *hist_cfg;
int ret = -1;
hist_cfg = kzalloc(sizeof(*hist_cfg), GFP_KERNEL);
if (hist_cfg == NULL)
return -ENOMEM;
memset(hist, 0, sizeof(*hist));
if (HIST_CONFIG_DMA)
ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, "DMA_ISP_HIST",
hist_dma_cb, hist, &hist->dma_ch);
if (ret) {
if (HIST_CONFIG_DMA)
dev_warn(isp->dev, "hist: DMA request channel failed. "
"Using PIO only.\n");
hist->dma_ch = -1;
} else {
dev_dbg(isp->dev, "hist: DMA channel = %d\n", hist->dma_ch);
hist_dma_config(hist);
omap_enable_dma_irq(hist->dma_ch, OMAP_DMA_BLOCK_IRQ);
}
hist->ops = &hist_ops;
hist->priv = hist_cfg;
hist->event_type = V4L2_EVENT_OMAP3ISP_HIST;
hist->isp = isp;
ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops);
if (ret) {
kfree(hist_cfg);
if (HIST_USING_DMA(hist))
omap_free_dma(hist->dma_ch);
}
return ret;
}
/*
* omap3isp_hist_cleanup - Module cleanup.
*/
void omap3isp_hist_cleanup(struct isp_device *isp)
{
if (HIST_USING_DMA(&isp->isp_hist))
omap_free_dma(isp->isp_hist.dma_ch);
kfree(isp->isp_hist.priv);
omap3isp_stat_cleanup(&isp->isp_hist);
}

40
drivers/media/platform/omap3isp/isphist.h Normal file
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/*
* isphist.h
*
* TI OMAP3 ISP - Histogram module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: David Cohen <dacohen@gmail.com>
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_HIST_H
#define OMAP3_ISP_HIST_H
#include <linux/omap3isp.h>
#define ISPHIST_IN_BIT_WIDTH_CCDC 10
struct isp_device;
int omap3isp_hist_init(struct isp_device *isp);
void omap3isp_hist_cleanup(struct isp_device *isp);
#endif /* OMAP3_ISP_HIST */

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drivers/media/platform/omap3isp/isppreview.c Normal file
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drivers/media/platform/omap3isp/isppreview.h Normal file
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/*
* isppreview.h
*
* TI OMAP3 ISP - Preview module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_PREVIEW_H
#define OMAP3_ISP_PREVIEW_H
#include <linux/omap3isp.h>
#include <linux/types.h>
#include <media/v4l2-ctrls.h>
#include "ispvideo.h"
#define ISPPRV_BRIGHT_STEP 0x1
#define ISPPRV_BRIGHT_DEF 0x0
#define ISPPRV_BRIGHT_LOW 0x0
#define ISPPRV_BRIGHT_HIGH 0xFF
#define ISPPRV_BRIGHT_UNITS 0x1
#define ISPPRV_CONTRAST_STEP 0x1
#define ISPPRV_CONTRAST_DEF 0x10
#define ISPPRV_CONTRAST_LOW 0x0
#define ISPPRV_CONTRAST_HIGH 0xFF
#define ISPPRV_CONTRAST_UNITS 0x1
/* Additional features not listed in linux/omap3isp.h */
#define OMAP3ISP_PREV_CONTRAST (1 << 17)
#define OMAP3ISP_PREV_BRIGHTNESS (1 << 18)
#define OMAP3ISP_PREV_FEATURES_END (1 << 19)
enum preview_input_entity {
PREVIEW_INPUT_NONE,
PREVIEW_INPUT_CCDC,
PREVIEW_INPUT_MEMORY,
};
#define PREVIEW_OUTPUT_RESIZER (1 << 1)
#define PREVIEW_OUTPUT_MEMORY (1 << 2)
/* Configure byte layout of YUV image */
enum preview_ycpos_mode {
YCPOS_YCrYCb = 0,
YCPOS_YCbYCr = 1,
YCPOS_CbYCrY = 2,
YCPOS_CrYCbY = 3
};
/*
* struct prev_params - Structure for all configuration
* @busy: Bitmask of busy parameters (being updated or used)
* @update: Bitmask of the parameters to be updated
* @features: Set of features enabled.
* @cfa: CFA coefficients.
* @csup: Chroma suppression coefficients.
* @luma: Luma enhancement coefficients.
* @nf: Noise filter coefficients.
* @dcor: Noise filter coefficients.
* @gamma: Gamma coefficients.
* @wbal: White Balance parameters.
* @blkadj: Black adjustment parameters.
* @rgb2rgb: RGB blending parameters.
* @csc: Color space conversion (RGB to YCbCr) parameters.
* @hmed: Horizontal median filter.
* @yclimit: YC limits parameters.
* @contrast: Contrast.
* @brightness: Brightness.
*/
struct prev_params {
u32 busy;
u32 update;
u32 features;
struct omap3isp_prev_cfa cfa;
struct omap3isp_prev_csup csup;
struct omap3isp_prev_luma luma;
struct omap3isp_prev_nf nf;
struct omap3isp_prev_dcor dcor;
struct omap3isp_prev_gtables gamma;
struct omap3isp_prev_wbal wbal;
struct omap3isp_prev_blkadj blkadj;
struct omap3isp_prev_rgbtorgb rgb2rgb;
struct omap3isp_prev_csc csc;
struct omap3isp_prev_hmed hmed;
struct omap3isp_prev_yclimit yclimit;
u8 contrast;
u8 brightness;
};
/* Sink and source previewer pads */
#define PREV_PAD_SINK 0
#define PREV_PAD_SOURCE 1
#define PREV_PADS_NUM 2
/*
* struct isp_prev_device - Structure for storing ISP Preview module information
* @subdev: V4L2 subdevice
* @pads: Media entity pads
* @formats: Active formats at the subdev pad
* @crop: Active crop rectangle
* @input: Module currently connected to the input pad
* @output: Bitmask of the active output
* @video_in: Input video entity
* @video_out: Output video entity
* @params.params : Active and shadow parameters sets
* @params.active: Bitmask of parameters active in set 0
* @params.lock: Parameters lock, protects params.active and params.shadow
* @underrun: Whether the preview entity has queued buffers on the output
* @state: Current preview pipeline state
*
* This structure is used to store the OMAP ISP Preview module Information.
*/
struct isp_prev_device {
struct v4l2_subdev subdev;
struct media_pad pads[PREV_PADS_NUM];
struct v4l2_mbus_framefmt formats[PREV_PADS_NUM];
struct v4l2_rect crop;
struct v4l2_ctrl_handler ctrls;
enum preview_input_entity input;
unsigned int output;
struct isp_video video_in;
struct isp_video video_out;
struct {
unsigned int cfa_order;
struct prev_params params[2];
u32 active;
spinlock_t lock;
} params;
enum isp_pipeline_stream_state state;
wait_queue_head_t wait;
atomic_t stopping;
};
struct isp_device;
int omap3isp_preview_init(struct isp_device *isp);
void omap3isp_preview_cleanup(struct isp_device *isp);
int omap3isp_preview_register_entities(struct isp_prev_device *prv,
struct v4l2_device *vdev);
void omap3isp_preview_unregister_entities(struct isp_prev_device *prv);
void omap3isp_preview_isr_frame_sync(struct isp_prev_device *prev);
void omap3isp_preview_isr(struct isp_prev_device *prev);
int omap3isp_preview_busy(struct isp_prev_device *isp_prev);
void omap3isp_preview_restore_context(struct isp_device *isp);
#endif /* OMAP3_ISP_PREVIEW_H */

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drivers/media/platform/omap3isp/ispqueue.h Normal file
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/*
* ispqueue.h
*
* TI OMAP3 ISP - Video buffers queue handling
*
* Copyright (C) 2010 Nokia Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_QUEUE_H
#define OMAP3_ISP_QUEUE_H
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/videodev2.h>
#include <linux/wait.h>
struct isp_video_queue;
struct page;
struct scatterlist;
#define ISP_VIDEO_MAX_BUFFERS 16
/**
* enum isp_video_buffer_state - ISP video buffer state
* @ISP_BUF_STATE_IDLE: The buffer is under userspace control (dequeued
* or not queued yet).
* @ISP_BUF_STATE_QUEUED: The buffer has been queued but isn't used by the
* device yet.
* @ISP_BUF_STATE_ACTIVE: The buffer is in use for an active video transfer.
* @ISP_BUF_STATE_ERROR: The device is done with the buffer and an error
* occurred. For capture device the buffer likely contains corrupted data or
* no data at all.
* @ISP_BUF_STATE_DONE: The device is done with the buffer and no error occurred.
* For capture devices the buffer contains valid data.
*/
enum isp_video_buffer_state {
ISP_BUF_STATE_IDLE,
ISP_BUF_STATE_QUEUED,
ISP_BUF_STATE_ACTIVE,
ISP_BUF_STATE_ERROR,
ISP_BUF_STATE_DONE,
};
/**
* struct isp_video_buffer - ISP video buffer
* @vma_use_count: Number of times the buffer is mmap'ed to userspace
* @stream: List head for insertion into main queue
* @queue: ISP buffers queue this buffer belongs to
* @prepared: Whether the buffer has been prepared
* @skip_cache: Whether to skip cache management operations for this buffer
* @vaddr: Memory virtual address (for kernel buffers)
* @vm_flags: Buffer VMA flags (for userspace buffers)
* @offset: Offset inside the first page (for userspace buffers)
* @npages: Number of pages (for userspace buffers)
* @pages: Pages table (for userspace non-VM_PFNMAP buffers)
* @paddr: Memory physical address (for userspace VM_PFNMAP buffers)
* @sglen: Number of elements in the scatter list (for non-VM_PFNMAP buffers)
* @sglist: Scatter list (for non-VM_PFNMAP buffers)
* @vbuf: V4L2 buffer
* @irqlist: List head for insertion into IRQ queue
* @state: Current buffer state
* @wait: Wait queue to signal buffer completion
*/
struct isp_video_buffer {
unsigned long vma_use_count;
struct list_head stream;
struct isp_video_queue *queue;
unsigned int prepared:1;
bool skip_cache;
/* For kernel buffers. */
void *vaddr;
/* For userspace buffers. */
vm_flags_t vm_flags;
unsigned long offset;
unsigned int npages;
struct page **pages;
dma_addr_t paddr;
/* For all buffers except VM_PFNMAP. */
unsigned int sglen;
struct scatterlist *sglist;
/* Touched by the interrupt handler. */
struct v4l2_buffer vbuf;
struct list_head irqlist;
enum isp_video_buffer_state state;
wait_queue_head_t wait;
};
#define to_isp_video_buffer(vb) container_of(vb, struct isp_video_buffer, vb)
/**
* struct isp_video_queue_operations - Driver-specific operations
* @queue_prepare: Called before allocating buffers. Drivers should clamp the
* number of buffers according to their requirements, and must return the
* buffer size in bytes.
* @buffer_prepare: Called the first time a buffer is queued, or after changing
* the userspace memory address for a USERPTR buffer, with the queue lock
* held. Drivers should perform device-specific buffer preparation (such as
* mapping the buffer memory in an IOMMU). This operation is optional.
* @buffer_queue: Called when a buffer is being added to the queue with the
* queue irqlock spinlock held.
* @buffer_cleanup: Called before freeing buffers, or before changing the
* userspace memory address for a USERPTR buffer, with the queue lock held.
* Drivers must perform cleanup operations required to undo the
* buffer_prepare call. This operation is optional.
*/
struct isp_video_queue_operations {
void (*queue_prepare)(struct isp_video_queue *queue,
unsigned int *nbuffers, unsigned int *size);
int (*buffer_prepare)(struct isp_video_buffer *buf);
void (*buffer_queue)(struct isp_video_buffer *buf);
void (*buffer_cleanup)(struct isp_video_buffer *buf);
};
/**
* struct isp_video_queue - ISP video buffers queue
* @type: Type of video buffers handled by this queue
* @ops: Queue operations
* @dev: Device used for DMA operations
* @bufsize: Size of a driver-specific buffer object
* @count: Number of currently allocated buffers
* @buffers: ISP video buffers
* @lock: Mutex to protect access to the buffers, main queue and state
* @irqlock: Spinlock to protect access to the IRQ queue
* @streaming: Queue state, indicates whether the queue is streaming
* @queue: List of all queued buffers
*/
struct isp_video_queue {
enum v4l2_buf_type type;
const struct isp_video_queue_operations *ops;
struct device *dev;
unsigned int bufsize;
unsigned int count;
struct isp_video_buffer *buffers[ISP_VIDEO_MAX_BUFFERS];
struct mutex lock;
spinlock_t irqlock;
unsigned int streaming:1;
struct list_head queue;
};
int omap3isp_video_queue_cleanup(struct isp_video_queue *queue);
int omap3isp_video_queue_init(struct isp_video_queue *queue,
enum v4l2_buf_type type,
const struct isp_video_queue_operations *ops,
struct device *dev, unsigned int bufsize);
int omap3isp_video_queue_reqbufs(struct isp_video_queue *queue,
struct v4l2_requestbuffers *rb);
int omap3isp_video_queue_querybuf(struct isp_video_queue *queue,
struct v4l2_buffer *vbuf);
int omap3isp_video_queue_qbuf(struct isp_video_queue *queue,
struct v4l2_buffer *vbuf);
int omap3isp_video_queue_dqbuf(struct isp_video_queue *queue,
struct v4l2_buffer *vbuf, int nonblocking);
int omap3isp_video_queue_streamon(struct isp_video_queue *queue);
void omap3isp_video_queue_streamoff(struct isp_video_queue *queue);
void omap3isp_video_queue_discard_done(struct isp_video_queue *queue);
int omap3isp_video_queue_mmap(struct isp_video_queue *queue,
struct vm_area_struct *vma);
unsigned int omap3isp_video_queue_poll(struct isp_video_queue *queue,
struct file *file, poll_table *wait);
#endif /* OMAP3_ISP_QUEUE_H */

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drivers/media/platform/omap3isp/ispresizer.c Normal file
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/*
* ispresizer.h
*
* TI OMAP3 ISP - Resizer module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_RESIZER_H
#define OMAP3_ISP_RESIZER_H
#include <linux/types.h>
/*
* Constants for filter coefficents count
*/
#define COEFF_CNT 32
/*
* struct isprsz_coef - Structure for resizer filter coeffcients.
* @h_filter_coef_4tap: Horizontal filter coefficients for 8-phase/4-tap
* mode (.5x-4x)
* @v_filter_coef_4tap: Vertical filter coefficients for 8-phase/4-tap
* mode (.5x-4x)
* @h_filter_coef_7tap: Horizontal filter coefficients for 4-phase/7-tap
* mode (.25x-.5x)
* @v_filter_coef_7tap: Vertical filter coefficients for 4-phase/7-tap
* mode (.25x-.5x)
*/
struct isprsz_coef {
u16 h_filter_coef_4tap[32];
u16 v_filter_coef_4tap[32];
/* Every 8th value is a dummy value in the following arrays: */
u16 h_filter_coef_7tap[32];
u16 v_filter_coef_7tap[32];
};
/* Chrominance horizontal algorithm */
enum resizer_chroma_algo {
RSZ_THE_SAME = 0, /* Chrominance the same as Luminance */
RSZ_BILINEAR = 1, /* Chrominance uses bilinear interpolation */
};
/* Resizer input type select */
enum resizer_colors_type {
RSZ_YUV422 = 0, /* YUV422 color is interleaved */
RSZ_COLOR8 = 1, /* Color separate data on 8 bits */
};
/*
* Structure for horizontal and vertical resizing value
*/
struct resizer_ratio {
u32 horz;
u32 vert;
};
/*
* Structure for luminance enhancer parameters.
*/
struct resizer_luma_yenh {
u8 algo; /* algorithm select. */
u8 gain; /* maximum gain. */
u8 slope; /* slope. */
u8 core; /* core offset. */
};
enum resizer_input_entity {
RESIZER_INPUT_NONE,
RESIZER_INPUT_VP, /* input video port - prev or ccdc */
RESIZER_INPUT_MEMORY,
};
/* Sink and source resizer pads */
#define RESZ_PAD_SINK 0
#define RESZ_PAD_SOURCE 1
#define RESZ_PADS_NUM 2
/*
* struct isp_res_device - OMAP3 ISP resizer module
* @crop.request: Crop rectangle requested by the user
* @crop.active: Active crop rectangle (based on hardware requirements)
*/
struct isp_res_device {
struct v4l2_subdev subdev;
struct media_pad pads[RESZ_PADS_NUM];
struct v4l2_mbus_framefmt formats[RESZ_PADS_NUM];
enum resizer_input_entity input;
struct isp_video video_in;
struct isp_video video_out;
u32 addr_base; /* stored source buffer address in memory mode */
u32 crop_offset; /* additional offset for crop in memory mode */
struct resizer_ratio ratio;
int pm_state;
unsigned int applycrop:1;
enum isp_pipeline_stream_state state;
wait_queue_head_t wait;
atomic_t stopping;
struct {
struct v4l2_rect request;
struct v4l2_rect active;
} crop;
};
struct isp_device;
int omap3isp_resizer_init(struct isp_device *isp);
void omap3isp_resizer_cleanup(struct isp_device *isp);
int omap3isp_resizer_register_entities(struct isp_res_device *res,
struct v4l2_device *vdev);
void omap3isp_resizer_unregister_entities(struct isp_res_device *res);
void omap3isp_resizer_isr_frame_sync(struct isp_res_device *res);
void omap3isp_resizer_isr(struct isp_res_device *isp_res);
void omap3isp_resizer_max_rate(struct isp_res_device *res,
unsigned int *max_rate);
void omap3isp_resizer_suspend(struct isp_res_device *isp_res);
void omap3isp_resizer_resume(struct isp_res_device *isp_res);
int omap3isp_resizer_busy(struct isp_res_device *isp_res);
#endif /* OMAP3_ISP_RESIZER_H */

1102
drivers/media/platform/omap3isp/ispstat.c Normal file
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drivers/media/platform/omap3isp/ispstat.h Normal file
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/*
* ispstat.h
*
* TI OMAP3 ISP - Statistics core
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc
*
* Contacts: David Cohen <dacohen@gmail.com>
* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_STAT_H
#define OMAP3_ISP_STAT_H
#include <linux/types.h>
#include <linux/omap3isp.h>
#include <plat/dma.h>
#include <media/v4l2-event.h>
#include "isp.h"
#include "ispvideo.h"
#define STAT_MAX_BUFS 5
#define STAT_NEVENTS 8
#define STAT_BUF_DONE 0 /* Buffer is ready */
#define STAT_NO_BUF 1 /* An error has occurred */
#define STAT_BUF_WAITING_DMA 2 /* Histogram only: DMA is running */
struct ispstat;
struct ispstat_buffer {
unsigned long iommu_addr;
struct iovm_struct *iovm;
void *virt_addr;
dma_addr_t dma_addr;
struct timeval ts;
u32 buf_size;
u32 frame_number;
u16 config_counter;
u8 empty;
};
struct ispstat_ops {
/*
* Validate new params configuration.
* new_conf->buf_size value must be changed to the exact buffer size
* necessary for the new configuration if it's smaller.
*/
int (*validate_params)(struct ispstat *stat, void *new_conf);
/*
* Save new params configuration.
* stat->priv->buf_size value must be set to the exact buffer size for
* the new configuration.
* stat->update is set to 1 if new configuration is different than
* current one.
*/
void (*set_params)(struct ispstat *stat, void *new_conf);
/* Apply stored configuration. */
void (*setup_regs)(struct ispstat *stat, void *priv);
/* Enable/Disable module. */
void (*enable)(struct ispstat *stat, int enable);
/* Verify is module is busy. */
int (*busy)(struct ispstat *stat);
/* Used for specific operations during generic buf process task. */
int (*buf_process)(struct ispstat *stat);
};
enum ispstat_state_t {
ISPSTAT_DISABLED = 0,
ISPSTAT_DISABLING,
ISPSTAT_ENABLED,
ISPSTAT_ENABLING,
ISPSTAT_SUSPENDED,
};
struct ispstat {
struct v4l2_subdev subdev;
struct media_pad pad; /* sink pad */
/* Control */
unsigned configured:1;
unsigned update:1;
unsigned buf_processing:1;
unsigned sbl_ovl_recover:1;
u8 inc_config;
atomic_t buf_err;
enum ispstat_state_t state; /* enabling/disabling state */
struct omap_dma_channel_params dma_config;
struct isp_device *isp;
void *priv; /* pointer to priv config struct */
void *recover_priv; /* pointer to recover priv configuration */
struct mutex ioctl_lock; /* serialize private ioctl */
const struct ispstat_ops *ops;
/* Buffer */
u8 wait_acc_frames;
u16 config_counter;
u32 frame_number;
u32 buf_size;
u32 buf_alloc_size;
int dma_ch;
unsigned long event_type;
struct ispstat_buffer *buf;
struct ispstat_buffer *active_buf;
struct ispstat_buffer *locked_buf;
};
struct ispstat_generic_config {
/*
* Fields must be in the same order as in:
* - omap3isp_h3a_aewb_config
* - omap3isp_h3a_af_config
* - omap3isp_hist_config
*/
u32 buf_size;
u16 config_counter;
};
int omap3isp_stat_config(struct ispstat *stat, void *new_conf);
int omap3isp_stat_request_statistics(struct ispstat *stat,
struct omap3isp_stat_data *data);
int omap3isp_stat_init(struct ispstat *stat, const char *name,
const struct v4l2_subdev_ops *sd_ops);
void omap3isp_stat_cleanup(struct ispstat *stat);
int omap3isp_stat_subscribe_event(struct v4l2_subdev *subdev,
struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub);
int omap3isp_stat_unsubscribe_event(struct v4l2_subdev *subdev,
struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub);
int omap3isp_stat_s_stream(struct v4l2_subdev *subdev, int enable);
int omap3isp_stat_busy(struct ispstat *stat);
int omap3isp_stat_pcr_busy(struct ispstat *stat);
void omap3isp_stat_suspend(struct ispstat *stat);
void omap3isp_stat_resume(struct ispstat *stat);
int omap3isp_stat_enable(struct ispstat *stat, u8 enable);
void omap3isp_stat_sbl_overflow(struct ispstat *stat);
void omap3isp_stat_isr(struct ispstat *stat);
void omap3isp_stat_isr_frame_sync(struct ispstat *stat);
void omap3isp_stat_dma_isr(struct ispstat *stat);
int omap3isp_stat_register_entities(struct ispstat *stat,
struct v4l2_device *vdev);
void omap3isp_stat_unregister_entities(struct ispstat *stat);
#endif /* OMAP3_ISP_STAT_H */

1404
drivers/media/platform/omap3isp/ispvideo.c Normal file
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drivers/media/platform/omap3isp/ispvideo.h Normal file
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/*
* ispvideo.h
*
* TI OMAP3 ISP - Generic video node
*
* Copyright (C) 2009-2010 Nokia Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef OMAP3_ISP_VIDEO_H
#define OMAP3_ISP_VIDEO_H
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-fh.h>
#include "ispqueue.h"
#define ISP_VIDEO_DRIVER_NAME "ispvideo"
#define ISP_VIDEO_DRIVER_VERSION "0.0.2"
struct isp_device;
struct isp_video;
struct v4l2_mbus_framefmt;
struct v4l2_pix_format;
/*
* struct isp_format_info - ISP media bus format information
* @code: V4L2 media bus format code
* @truncated: V4L2 media bus format code for the same format truncated to 10
* bits. Identical to @code if the format is 10 bits wide or less.
* @uncompressed: V4L2 media bus format code for the corresponding uncompressed
* format. Identical to @code if the format is not DPCM compressed.
* @flavor: V4L2 media bus format code for the same pixel layout but
* shifted to be 8 bits per pixel. =0 if format is not shiftable.
* @pixelformat: V4L2 pixel format FCC identifier
* @width: Bits per pixel (when transferred over a bus)
* @bpp: Bytes per pixel (when stored in memory)
*/
struct isp_format_info {
enum v4l2_mbus_pixelcode code;
enum v4l2_mbus_pixelcode truncated;
enum v4l2_mbus_pixelcode uncompressed;
enum v4l2_mbus_pixelcode flavor;
u32 pixelformat;
unsigned int width;
unsigned int bpp;
};
enum isp_pipeline_stream_state {
ISP_PIPELINE_STREAM_STOPPED = 0,
ISP_PIPELINE_STREAM_CONTINUOUS = 1,
ISP_PIPELINE_STREAM_SINGLESHOT = 2,
};
enum isp_pipeline_state {
/* The stream has been started on the input video node. */
ISP_PIPELINE_STREAM_INPUT = 1,
/* The stream has been started on the output video node. */
ISP_PIPELINE_STREAM_OUTPUT = 2,
/* At least one buffer is queued on the input video node. */
ISP_PIPELINE_QUEUE_INPUT = 4,
/* At least one buffer is queued on the output video node. */
ISP_PIPELINE_QUEUE_OUTPUT = 8,
/* The input entity is idle, ready to be started. */
ISP_PIPELINE_IDLE_INPUT = 16,
/* The output entity is idle, ready to be started. */
ISP_PIPELINE_IDLE_OUTPUT = 32,
/* The pipeline is currently streaming. */
ISP_PIPELINE_STREAM = 64,
};
/*
* struct isp_pipeline - An ISP hardware pipeline
* @error: A hardware error occurred during capture
* @entities: Bitmask of entities in the pipeline (indexed by entity ID)
*/
struct isp_pipeline {
struct media_pipeline pipe;
spinlock_t lock; /* Pipeline state and queue flags */
unsigned int state;
enum isp_pipeline_stream_state stream_state;
struct isp_video *input;
struct isp_video *output;
u32 entities;
unsigned long l3_ick;
unsigned int max_rate;
atomic_t frame_number;
bool do_propagation; /* of frame number */
bool error;
struct v4l2_fract max_timeperframe;
struct v4l2_subdev *external;
unsigned int external_rate;
unsigned int external_width;
};
#define to_isp_pipeline(__e) \
container_of((__e)->pipe, struct isp_pipeline, pipe)
static inline int isp_pipeline_ready(struct isp_pipeline *pipe)
{
return pipe->state == (ISP_PIPELINE_STREAM_INPUT |
ISP_PIPELINE_STREAM_OUTPUT |
ISP_PIPELINE_QUEUE_INPUT |
ISP_PIPELINE_QUEUE_OUTPUT |
ISP_PIPELINE_IDLE_INPUT |
ISP_PIPELINE_IDLE_OUTPUT);
}
/*
* struct isp_buffer - ISP buffer
* @buffer: ISP video buffer
* @isp_addr: MMU mapped address (a.k.a. device address) of the buffer.
*/
struct isp_buffer {
struct isp_video_buffer buffer;
dma_addr_t isp_addr;
};
#define to_isp_buffer(buf) container_of(buf, struct isp_buffer, buffer)
enum isp_video_dmaqueue_flags {
/* Set if DMA queue becomes empty when ISP_PIPELINE_STREAM_CONTINUOUS */
ISP_VIDEO_DMAQUEUE_UNDERRUN = (1 << 0),
/* Set when queuing buffer to an empty DMA queue */
ISP_VIDEO_DMAQUEUE_QUEUED = (1 << 1),
};
#define isp_video_dmaqueue_flags_clr(video) \
({ (video)->dmaqueue_flags = 0; })
/*
* struct isp_video_operations - ISP video operations
* @queue: Resume streaming when a buffer is queued. Called on VIDIOC_QBUF
* if there was no buffer previously queued.
*/
struct isp_video_operations {
int(*queue)(struct isp_video *video, struct isp_buffer *buffer);
};
struct isp_video {
struct video_device video;
enum v4l2_buf_type type;
struct media_pad pad;
struct mutex mutex; /* format and crop settings */
atomic_t active;
struct isp_device *isp;
unsigned int capture_mem;
unsigned int bpl_alignment; /* alignment value */
unsigned int bpl_zero_padding; /* whether the alignment is optional */
unsigned int bpl_max; /* maximum bytes per line value */
unsigned int bpl_value; /* bytes per line value */
unsigned int bpl_padding; /* padding at end of line */
/* Entity video node streaming */
unsigned int streaming:1;
/* Pipeline state */
struct isp_pipeline pipe;
struct mutex stream_lock; /* pipeline and stream states */
/* Video buffers queue */
struct isp_video_queue *queue;
struct list_head dmaqueue;
enum isp_video_dmaqueue_flags dmaqueue_flags;
const struct isp_video_operations *ops;
};
#define to_isp_video(vdev) container_of(vdev, struct isp_video, video)
struct isp_video_fh {
struct v4l2_fh vfh;
struct isp_video *video;
struct isp_video_queue queue;
struct v4l2_format format;
struct v4l2_fract timeperframe;
};
#define to_isp_video_fh(fh) container_of(fh, struct isp_video_fh, vfh)
#define isp_video_queue_to_isp_video_fh(q) \
container_of(q, struct isp_video_fh, queue)
int omap3isp_video_init(struct isp_video *video, const char *name);
void omap3isp_video_cleanup(struct isp_video *video);
int omap3isp_video_register(struct isp_video *video,
struct v4l2_device *vdev);
void omap3isp_video_unregister(struct isp_video *video);
struct isp_buffer *omap3isp_video_buffer_next(struct isp_video *video);
void omap3isp_video_resume(struct isp_video *video, int continuous);
struct media_pad *omap3isp_video_remote_pad(struct isp_video *video);
const struct isp_format_info *
omap3isp_video_format_info(enum v4l2_mbus_pixelcode code);
#endif /* OMAP3_ISP_VIDEO_H */

42
drivers/media/platform/omap3isp/luma_enhance_table.h Normal file
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/*
* luma_enhance_table.h
*
* TI OMAP3 ISP - Luminance enhancement table
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
1047552, 1047552, 1047552, 1047552, 1047552, 1047552, 1047552, 1047552,
1047552, 1047552, 1047552, 1047552, 1047552, 1047552, 1047552, 1047552,
1047552, 1047552, 1047552, 1047552, 1047552, 1047552, 1047552, 1047552,
1047552, 1047552, 1047552, 1047552, 1048575, 1047551, 1046527, 1045503,
1044479, 1043455, 1042431, 1041407, 1040383, 1039359, 1038335, 1037311,
1036287, 1035263, 1034239, 1033215, 1032191, 1031167, 1030143, 1028096,
1028096, 1028096, 1028096, 1028096, 1028096, 1028096, 1028096, 1028096,
1028096, 1028100, 1032196, 1036292, 1040388, 1044484, 0, 0,
0, 5, 5125, 10245, 15365, 20485, 25605, 30720,
30720, 30720, 30720, 30720, 30720, 30720, 30720, 30720,
30720, 30720, 31743, 30719, 29695, 28671, 27647, 26623,
25599, 24575, 23551, 22527, 21503, 20479, 19455, 18431,
17407, 16383, 15359, 14335, 13311, 12287, 11263, 10239,
9215, 8191, 7167, 6143, 5119, 4095, 3071, 1024,
1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024

30
drivers/media/platform/omap3isp/noise_filter_table.h Normal file
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/*
* noise_filter_table.h
*
* TI OMAP3 ISP - Noise filter table
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31