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Merge branch 'remotes/lorenzo/pci/keystone'

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- Move IRQ register address computation inside macros (Kishon Vijay
    Abraham I)

  - Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I)

  - Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham
    I)

  - Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon
    Vijay Abraham I)

  - Add dwc support for platforms with custom MSI controllers (Kishon Vijay
    Abraham I)

  - Add keystone-specific MSI controller (Kishon Vijay Abraham I)

  - Remove dwc host_ops previously used for keystone-specific MSI (Kishon
    Vijay Abraham I)

  - Skip dwc default MSI init if platform has custom MSI controller (Kishon
    Vijay Abraham I)

  - Implement .start_link() and .stop_link() for keystone endpoint support
    (Kishon Vijay Abraham I)

  - Add keystone "reg-names" DT binding (Kishon Vijay Abraham I)

  - Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon
    Vijay Abraham I)

  - Get keystone register resources from DT by name, not index (Kishon
    Vijay Abraham I)

  - Get DT resources in .probe() to prepare for endpoint support (Kishon
    Vijay Abraham I)

  - Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration
    (Kishon Vijay Abraham I)

  - Explicitly set keystone to host mode (Kishon Vijay Abraham I)

  - Document DT "atu" reg-names requirement for DesignWare core >= 4.80
    (Kishon Vijay Abraham I)

  - Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon
    Vijay Abraham I)

  - Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon
    Vijay Abraham I)

  - Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham
    I)

  - Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham
    I)

  - Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I)

  - Reset keystone PHYs before enabling them (Kishon Vijay Abraham I)

  - Make of_pci_get_max_link_speed() available to endpoint drivers as well
    as host drivers (Kishon Vijay Abraham I)

  - Add keystone support for DT "max-link-speed" property (Kishon Vijay
    Abraham I)

  - Add endpoint library support for BAR buffer alignment (Kishon Vijay
    Abraham I)

  - Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I)

  - Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay
    Abraham I)

  - Add dwc hooks for dbi/dbi2 that share the same address space (Kishon
    Vijay Abraham I)

  - Add keystone support for TI AM654x in endpoint mode (Kishon Vijay
    Abraham I)

  - Configure designware endpoints to advertise smallest resizable BAR
    (1MB) (Kishon Vijay Abraham I)

  - Align designware endpoint ATU windows for raising MSIs (Kishon Vijay
    Abraham I)

  - Add endpoint test support for TI AM654x (Kishon Vijay Abraham I)

  - Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/keystone:
  misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test
  misc: pci_endpoint_test: Add support to test PCI EP in AM654x
  PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
  PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
  PCI: keystone: Add support for PCIe EP in AM654x Platforms
  dt-bindings: PCI: Add PCI EP DT binding documentation for AM654
  PCI: dwc: Add callbacks for accessing dbi2 address space
  PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset
  PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
  PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
  PCI: keystone: Add support to set the max link speed from DT
  PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers
  PCI: keystone: Invoke phy_reset() API before enabling PHY
  PCI: keystone: Add support for PCIe RC in AM654x Platforms
  dt-bindings: PCI: Add PCI RC DT binding documentation for AM654
  PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
  PCI: dwc: Fix ATU identification for designware version >= 4.80
  PCI: dwc: Enable iATU unroll for endpoint too
  dt-bindings: PCI: Document "atu" reg-names
  PCI: keystone: Explicitly set the PCIe mode
  dt-bindings: PCI: Add dt-binding to configure PCIe mode
  PCI: keystone: Move resources initialization to prepare for EP support
  PCI: keystone: Use platform_get_resource_byname() to get memory resources
  PCI: keystone: Perform host initialization in a single function
  dt-bindings: PCI: keystone: Add "reg-names" binding information
  PCI: keystone: Cleanup error_irq configuration
  PCI: keystone: Add start_link()/stop_link() dw_pcie_ops
  PCI: dwc: Remove default MSI initialization for platform specific MSI chips
  PCI: dwc: Remove Keystone specific dw_pcie_host_ops
  PCI: keystone: Use Keystone specific msi_irq_chip
  PCI: dwc: Add support to use non default msi_irq_chip
  PCI: keystone: Cleanup ks_pcie_msi_irq_handler()
  PCI: keystone: Use hwirq to get the MSI IRQ number offset
  PCI: keystone: Add separate functions for configuring MSI and legacy interrupt
  PCI: keystone: Cleanup interrupt related macros

# Conflicts:
#	drivers/pci/controller/dwc/pcie-designware.h
This commit is contained in:
Bjorn Helgaas
2019-05-13 18:34:41 -05:00
parent b138f67d7b 8f22066457
commit 0b8439d374
19 changed files with 966 additions and 399 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/pci/controller/dwc/pcie-designware.h
View File

@@ -148,14 +148,9 @@ struct dw_pcie_host_ops {
int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
unsigned int devfn, int where, int size, u32 val);
int (*host_init)(struct pcie_port *pp);
void (*msi_set_irq)(struct pcie_port *pp, int irq);
void (*msi_clear_irq)(struct pcie_port *pp, int irq);
phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
u32 (*get_msi_data)(struct pcie_port *pp, int pos);
void (*scan_bus)(struct pcie_port *pp);
void (*set_num_vectors)(struct pcie_port *pp);
int (*msi_host_init)(struct pcie_port *pp);
void (*msi_irq_ack)(int irq, struct pcie_port *pp);
};
struct pcie_port {
@@ -183,6 +178,7 @@ struct pcie_port {
struct irq_domain *msi_domain;
dma_addr_t msi_data;
struct page *msi_page;
struct irq_chip *msi_irq_chip;
u32 num_vectors;
u32 irq_mask[MAX_MSI_CTRLS];
struct pci_bus *root_bus;
@@ -205,7 +201,7 @@ struct dw_pcie_ep_ops {
struct dw_pcie_ep {
struct pci_epc *epc;
struct dw_pcie_ep_ops *ops;
const struct dw_pcie_ep_ops *ops;
phys_addr_t phys_base;
size_t addr_size;
size_t page_size;
@@ -227,6 +223,10 @@ struct dw_pcie_ops {
size_t size);
void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
size_t size, u32 val);
u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
size_t size);
void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
size_t size, u32 val);
int (*link_up)(struct dw_pcie *pcie);
int (*start_link)(struct dw_pcie *pcie);
void (*stop_link)(struct dw_pcie *pcie);
@@ -243,6 +243,7 @@ struct dw_pcie {
struct pcie_port pp;
struct dw_pcie_ep ep;
const struct dw_pcie_ops *ops;
unsigned int version;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
@@ -257,6 +258,10 @@ u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
size_t size);
void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
size_t size, u32 val);
u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg,
size_t size);
void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg,
size_t size, u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
@@ -300,12 +305,12 @@ static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
{
__dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val);
__dw_pcie_write_dbi2(pci, pci->dbi_base2, reg, 0x4, val);
}
static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
{
return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
return __dw_pcie_read_dbi2(pci, pci->dbi_base2, reg, 0x4);
}
static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)