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ath9k_hw: Configure pll control register accordingly for AR9340

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Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
2011-04-20 10:26:15 +05:30
committed by John W. Linville
parent f2f5f2a1ce
commit 0b488ac6ec
4 changed files with 56 additions and 3 deletions
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3
drivers/net/wireless/ath/ath9k/phy.h
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@@ -45,4 +45,7 @@
#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
#define AR_PHY_PLL_CONTROL 0x16180
#define AR_PHY_PLL_MODE 0x16184
#endif