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Merge branch 'late/fixes' into fixes

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This is a series from Arnd that fixes a number of compiler warnings
when building defconfigs on ARM.

* late/fixes:
  ARM: footbridge: nw_gpio_lock is raw_spin_lock
  ARM: mv78xx0: correct addr_map_cfg __initdata annotation
  ARM: footbridge: remove RTC_IRQ definition
  ARM: soc: dependency warnings for errata
  ARM: ks8695: __arch_virt_to_dma type handling
  ARM: rpc: check device_register return code in ecard_probe
  ARM: davinci: don't mark da850_register_cpufreq as __init
  ARM: iop13xx: fix iq81340sc_atux_map_irq prototype
  ARM: iop13xx: mark iop13xx_scan_bus as __devinit
  ARM: mv78xx0: mark mv78xx0_timer_init as __init_refok
  ARM: s3c24xx: fix multiple section mismatch warnings
  ARM: at91: unused variable in at91_pm_verify_clocks
  ARM: at91: skip at91_io_desc definition for NOMMU
  ARM: pxa: work around duplicate definition of GPIO24_SSP1_SFRM
  ARM: pxa: remove sharpsl_fatal_check function
  ARM: pxa: define palmte2_pxa_keys conditionally
  ARM: pxa: Wunused-result warning in viper board file
  ARM: shark: fix shark_pci_init return code

Fixed trivial conflicts in arch/arm/mach-at91/setup.c.

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2012-10-07 07:22:32 -07:00
parent a4ee7770c4 45ef6ac6f5
commit 0b33162ec5
23 changed files with 37 additions and 81 deletions
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4
drivers/char/nwflash.c
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@@ -583,9 +583,9 @@ static void kick_open(void)
* we want to write a bit pattern XXX1 to Xilinx to enable
* the write gate, which will be open for about the next 2ms.
*/
spin_lock_irqsave(&nw_gpio_lock, flags);
raw_spin_lock_irqsave(&nw_gpio_lock, flags);
nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
/*
* let the ISA bus to catch on...