Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cleanups from Ingo Molnar: "Misc cleanups" * 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/apm: Fix spelling mistake: "caculate" -> "calculate" x86/mtrr: Rename main.c to mtrr.c and remove duplicate prefixes x86: Remove pr_fmt duplicate logging prefixes x86/early-quirks: Rename duplicate define of dev_err x86/bpf: Clean up non-standard comments, to make the code more readable
This commit is contained in:
@@ -2433,7 +2433,7 @@ MODULE_PARM_DESC(idle_threshold,
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"System idle percentage above which to make APM BIOS idle calls");
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module_param(idle_period, int, 0444);
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MODULE_PARM_DESC(idle_period,
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"Period (in sec/100) over which to caculate the idle percentage");
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"Period (in sec/100) over which to calculate the idle percentage");
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module_param(smp, bool, 0444);
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MODULE_PARM_DESC(smp,
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"Set this to enable APM use on an SMP platform. Use with caution on older systems");
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@@ -1,3 +1,3 @@
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obj-y := main.o if.o generic.o cleanup.o
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obj-y := mtrr.o if.o generic.o cleanup.o
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obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o
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@@ -101,7 +101,7 @@ static int have_wrcomb(void)
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if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
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dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
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dev->revision <= 5) {
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pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
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pr_info("Serverworks LE rev < 6 detected. Write-combining disabled.\n");
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pci_dev_put(dev);
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return 0;
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}
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@@ -111,7 +111,7 @@ static int have_wrcomb(void)
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*/
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if (dev->vendor == PCI_VENDOR_ID_INTEL &&
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dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
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pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
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pr_info("Intel 450NX MMC detected. Write-combining disabled.\n");
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pci_dev_put(dev);
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return 0;
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}
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@@ -313,24 +313,24 @@ int mtrr_add_page(unsigned long base, unsigned long size,
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return error;
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if (type >= MTRR_NUM_TYPES) {
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pr_warn("mtrr: type: %u invalid\n", type);
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pr_warn("type: %u invalid\n", type);
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return -EINVAL;
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}
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/* If the type is WC, check that this processor supports it */
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if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
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pr_warn("mtrr: your processor doesn't support write-combining\n");
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pr_warn("your processor doesn't support write-combining\n");
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return -ENOSYS;
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}
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if (!size) {
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pr_warn("mtrr: zero sized request\n");
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pr_warn("zero sized request\n");
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return -EINVAL;
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}
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if ((base | (base + size - 1)) >>
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(boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {
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pr_warn("mtrr: base or size exceeds the MTRR width\n");
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pr_warn("base or size exceeds the MTRR width\n");
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return -EINVAL;
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}
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@@ -361,8 +361,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
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} else if (types_compatible(type, ltype))
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continue;
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}
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pr_warn("mtrr: 0x%lx000,0x%lx000 overlaps existing"
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" 0x%lx000,0x%lx000\n", base, size, lbase,
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pr_warn("0x%lx000,0x%lx000 overlaps existing 0x%lx000,0x%lx000\n", base, size, lbase,
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lsize);
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goto out;
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}
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@@ -370,7 +369,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
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if (ltype != type) {
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if (types_compatible(type, ltype))
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continue;
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pr_warn("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
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pr_warn("type mismatch for %lx000,%lx000 old: %s new: %s\n",
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base, size, mtrr_attrib_to_str(ltype),
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mtrr_attrib_to_str(type));
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goto out;
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@@ -396,7 +395,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
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}
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}
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} else {
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pr_info("mtrr: no more MTRRs available\n");
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pr_info("no more MTRRs available\n");
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}
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error = i;
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out:
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@@ -408,8 +407,8 @@ int mtrr_add_page(unsigned long base, unsigned long size,
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static int mtrr_check(unsigned long base, unsigned long size)
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{
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if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
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pr_warn("mtrr: size and base must be multiples of 4 kiB\n");
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pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base);
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pr_warn("size and base must be multiples of 4 kiB\n");
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pr_debug("size: 0x%lx base: 0x%lx\n", size, base);
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dump_stack();
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return -1;
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}
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@@ -500,22 +499,22 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size)
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}
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}
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if (reg < 0) {
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pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n",
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pr_debug("no MTRR for %lx000,%lx000 found\n",
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base, size);
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goto out;
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}
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}
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if (reg >= max) {
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pr_warn("mtrr: register: %d too big\n", reg);
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pr_warn("register: %d too big\n", reg);
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goto out;
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}
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mtrr_if->get(reg, &lbase, &lsize, <ype);
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if (lsize < 1) {
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pr_warn("mtrr: MTRR %d not used\n", reg);
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pr_warn("MTRR %d not used\n", reg);
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goto out;
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}
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if (mtrr_usage_table[reg] < 1) {
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pr_warn("mtrr: reg: %d has count=0\n", reg);
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pr_warn("reg: %d has count=0\n", reg);
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goto out;
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}
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if (--mtrr_usage_table[reg] < 1)
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@@ -776,7 +775,7 @@ void __init mtrr_bp_init(void)
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}
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if (!mtrr_enabled()) {
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pr_info("MTRR: Disabled\n");
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pr_info("Disabled\n");
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/*
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* PAT initialization relies on MTRR's rendezvous handler.
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@@ -155,7 +155,8 @@ static void __init __e820__range_add(struct e820_table *table, u64 start, u64 si
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int x = table->nr_entries;
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if (x >= ARRAY_SIZE(table->entries)) {
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pr_err("e820: too many entries; ignoring [mem %#010llx-%#010llx]\n", start, start + size - 1);
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pr_err("too many entries; ignoring [mem %#010llx-%#010llx]\n",
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start, start + size - 1);
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return;
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}
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@@ -190,9 +191,10 @@ void __init e820__print_table(char *who)
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int i;
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for (i = 0; i < e820_table->nr_entries; i++) {
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pr_info("%s: [mem %#018Lx-%#018Lx] ", who,
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e820_table->entries[i].addr,
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e820_table->entries[i].addr + e820_table->entries[i].size - 1);
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pr_info("%s: [mem %#018Lx-%#018Lx] ",
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who,
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e820_table->entries[i].addr,
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e820_table->entries[i].addr + e820_table->entries[i].size - 1);
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e820_print_type(e820_table->entries[i].type);
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pr_cont("\n");
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@@ -574,7 +576,7 @@ void __init e820__update_table_print(void)
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if (e820__update_table(e820_table))
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return;
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pr_info("e820: modified physical RAM map:\n");
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pr_info("modified physical RAM map:\n");
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e820__print_table("modified");
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}
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@@ -636,9 +638,8 @@ __init void e820__setup_pci_gap(void)
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if (!found) {
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#ifdef CONFIG_X86_64
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gapstart = (max_pfn << PAGE_SHIFT) + 1024*1024;
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pr_err(
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"e820: Cannot find an available gap in the 32-bit address range\n"
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"e820: PCI devices with unassigned 32-bit BARs may not work!\n");
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pr_err("Cannot find an available gap in the 32-bit address range\n");
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pr_err("PCI devices with unassigned 32-bit BARs may not work!\n");
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#else
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gapstart = 0x10000000;
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#endif
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@@ -649,7 +650,8 @@ __init void e820__setup_pci_gap(void)
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*/
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pci_mem_start = gapstart;
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pr_info("e820: [mem %#010lx-%#010lx] available for PCI devices\n", gapstart, gapstart + gapsize - 1);
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pr_info("[mem %#010lx-%#010lx] available for PCI devices\n",
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gapstart, gapstart + gapsize - 1);
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}
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/*
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@@ -711,7 +713,7 @@ void __init e820__memory_setup_extended(u64 phys_addr, u32 data_len)
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memcpy(e820_table_firmware, e820_table, sizeof(*e820_table_firmware));
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early_memunmap(sdata, data_len);
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pr_info("e820: extended physical RAM map:\n");
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pr_info("extended physical RAM map:\n");
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e820__print_table("extended");
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}
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@@ -780,7 +782,7 @@ u64 __init e820__memblock_alloc_reserved(u64 size, u64 align)
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addr = __memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ACCESSIBLE);
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if (addr) {
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e820__range_update_kexec(addr, size, E820_TYPE_RAM, E820_TYPE_RESERVED);
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pr_info("e820: update e820_table_kexec for e820__memblock_alloc_reserved()\n");
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pr_info("update e820_table_kexec for e820__memblock_alloc_reserved()\n");
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e820__update_table_kexec();
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}
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@@ -830,8 +832,8 @@ static unsigned long __init e820_end_pfn(unsigned long limit_pfn, enum e820_type
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if (last_pfn > max_arch_pfn)
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last_pfn = max_arch_pfn;
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pr_info("e820: last_pfn = %#lx max_arch_pfn = %#lx\n",
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last_pfn, max_arch_pfn);
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pr_info("last_pfn = %#lx max_arch_pfn = %#lx\n",
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last_pfn, max_arch_pfn);
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return last_pfn;
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}
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@@ -1005,7 +1007,7 @@ void __init e820__finish_early_params(void)
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if (e820__update_table(e820_table) < 0)
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early_panic("Invalid user supplied memory map");
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pr_info("e820: user-defined physical RAM map:\n");
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pr_info("user-defined physical RAM map:\n");
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e820__print_table("user");
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}
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}
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@@ -1238,7 +1240,7 @@ void __init e820__memory_setup(void)
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memcpy(e820_table_kexec, e820_table, sizeof(*e820_table_kexec));
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memcpy(e820_table_firmware, e820_table, sizeof(*e820_table_firmware));
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pr_info("e820: BIOS-provided physical RAM map:\n");
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pr_info("BIOS-provided physical RAM map:\n");
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e820__print_table(who);
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}
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@@ -28,8 +28,6 @@
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#include <asm/irq_remapping.h>
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#include <asm/early_ioremap.h>
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#define dev_err(msg) pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg)
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static void __init fix_hypertransport_config(int num, int slot, int func)
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{
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u32 htcfg;
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@@ -617,7 +615,8 @@ static void __init apple_airport_reset(int bus, int slot, int func)
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pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
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if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
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dev_err("Cannot power up Apple AirPort card\n");
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pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n",
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bus, slot, func);
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return;
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}
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}
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@@ -628,7 +627,8 @@ static void __init apple_airport_reset(int bus, int slot, int func)
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mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
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if (!mmio) {
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dev_err("Cannot iomap Apple AirPort card\n");
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pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n",
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bus, slot, func);
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return;
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}
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@@ -975,8 +975,7 @@ int __init hpet_enable(void)
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cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
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hpet_writel(cfg, HPET_CFG);
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if (cfg)
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pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
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cfg);
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pr_warn("Unrecognized bits %#x set in global cfg\n", cfg);
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for (i = 0; i <= last; ++i) {
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cfg = hpet_readl(HPET_Tn_CFG(i));
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@@ -988,7 +987,7 @@ int __init hpet_enable(void)
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| HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
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| HPET_TN_FSB | HPET_TN_FSB_CAP);
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if (cfg)
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pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
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pr_warn("Unrecognized bits %#x set in cfg#%u\n",
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cfg, i);
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}
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hpet_print_config();
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@@ -1083,8 +1083,8 @@ arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs
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return orig_ret_vaddr;
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if (nleft != rasize) {
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pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
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"%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
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pr_err("return address clobbered: pid=%d, %%sp=%#lx, %%ip=%#lx\n",
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current->pid, regs->sp, regs->ip);
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force_sig_info(SIGSEGV, SEND_SIG_FORCED, current);
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}
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