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ASoC: tegra: fix I2S bit count mask

소스 검색 
This register field is 11 bits wide, not 15 bits wide. Given the way
this value is currently, used, this patch has no practical effect.
However, it's still best if the value is correct.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Stephen Warren
2013-03-04 17:10:20 -07:00
committed by Mark Brown
부모 6dbe51c251
커밋 0af18c5cc9
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sound/soc/tegra/tegra30_i2s.h
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@@ -110,7 +110,7 @@
#define TEGRA30_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7fff
#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff
#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
/* Fields in TEGRA30_I2S_OFFSET */