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Merge tag 'drm-misc-next-2018-04-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

Browse Source 
drm-misc-next for v4.18:

UAPI Changes:
- Add support for a generic plane alpha property to sun4i, rcar-du and atmel-hclcdc. (Maxime)

Core Changes:
- Stop looking at legacy plane->fb and crtc members in atomic drivers. (Ville)
- mode_valid return type fixes. (Luc)
- Handle zpos normalization in the core. (Peter)

Driver Changes:
- Implement CTM, plane alpha and generic async cursor support in vc4. (Stefan)
- Various fixes for HPD and aux chan in drm_bridge/analogix_dp. (Lin, Zain, Douglas)
- Add support for MIPI DSI to sun4i. (Maxime)

Signed-off-by: Dave Airlie <airlied@redhat.com>

# gpg: Signature made Thu 26 Apr 2018 08:21:01 PM AEST
# gpg:                using RSA key FE558C72A67013C3
# gpg: Can't check signature: public key not found
Link: https://patchwork.freedesktop.org/patch/msgid/b33da7eb-efc9-ae6f-6f69-b7acd6df6797@mblankhorst.nl
This commit is contained in:
Dave Airlie
2018-04-30 09:32:34 +10:00
parent 6da6c0db53 741c3aeb82
commit 0ab390262c
165 changed files with 8500 additions and 1097 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/drm/bridge/Kconfig
View File

@@ -25,6 +25,16 @@ config DRM_ANALOGIX_ANX78XX
the HDMI output of an application processor to MyDP
or DisplayPort.
config DRM_CDNS_DSI
tristate "Cadence DPI/DSI bridge"
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL_BRIDGE
depends on OF
help
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
@@ -93,6 +103,12 @@ config DRM_SII9234
It is an I2C driver, that detects connection of MHL bridge
and starts encapsulation of HDMI signal.
config DRM_THINE_THC63LVD1024
tristate "Thine THC63LVD1024 LVDS decoder bridge"
depends on OF
---help---
Thine THC63LVD1024 LVDS/parallel converter driver.
config DRM_TOSHIBA_TC358767
tristate "Toshiba TC358767 eDP bridge"
depends on OF

2
drivers/gpu/drm/bridge/Makefile
View File

@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o
@@ -8,6 +9,7 @@ obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_SII9234) += sii9234.o
obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o
obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/

6
drivers/gpu/drm/bridge/adv7511/adv7511.h
View File

@@ -93,6 +93,11 @@
#define ADV7511_REG_CHIP_ID_HIGH 0xf5
#define ADV7511_REG_CHIP_ID_LOW 0xf6
/* Hardware defined default addresses for I2C register maps */
#define ADV7511_CEC_I2C_ADDR_DEFAULT 0x3c
#define ADV7511_EDID_I2C_ADDR_DEFAULT 0x3f
#define ADV7511_PACKET_I2C_ADDR_DEFAULT 0x38
#define ADV7511_CSC_ENABLE BIT(7)
#define ADV7511_CSC_UPDATE_MODE BIT(5)
@@ -321,6 +326,7 @@ enum adv7511_type {
struct adv7511 {
struct i2c_client *i2c_main;
struct i2c_client *i2c_edid;
struct i2c_client *i2c_packet;
struct i2c_client *i2c_cec;
struct regmap *regmap;

44
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
View File

@@ -586,7 +586,7 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
/* Reading the EDID only works if the device is powered */
if (!adv7511->powered) {
unsigned int edid_i2c_addr =
(adv7511->i2c_main->addr << 1) + 4;
(adv7511->i2c_edid->addr << 1);
__adv7511_power_on(adv7511);
@@ -654,7 +654,7 @@ adv7511_detect(struct adv7511 *adv7511, struct drm_connector *connector)
return status;
}
static int adv7511_mode_valid(struct adv7511 *adv7511,
static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511,
struct drm_display_mode *mode)
{
if (mode->clock > 165000)
@@ -969,10 +969,10 @@ static int adv7511_init_cec_regmap(struct adv7511 *adv)
{
int ret;
adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
adv->i2c_main->addr - 1);
adv->i2c_cec = i2c_new_secondary_device(adv->i2c_main, "cec",
ADV7511_CEC_I2C_ADDR_DEFAULT);
if (!adv->i2c_cec)
return -ENOMEM;
return -EINVAL;
i2c_set_clientdata(adv->i2c_cec, adv);
adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
@@ -1082,8 +1082,6 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
struct adv7511_link_config link_config;
struct adv7511 *adv7511;
struct device *dev = &i2c->dev;
unsigned int main_i2c_addr = i2c->addr << 1;
unsigned int edid_i2c_addr = main_i2c_addr + 4;
unsigned int val;
int ret;
@@ -1153,23 +1151,34 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
if (ret)
goto uninit_regulators;
regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, edid_i2c_addr);
regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR,
main_i2c_addr - 0xa);
regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR,
main_i2c_addr - 2);
adv7511_packet_disable(adv7511, 0xffff);
adv7511->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1);
adv7511->i2c_edid = i2c_new_secondary_device(i2c, "edid",
ADV7511_EDID_I2C_ADDR_DEFAULT);
if (!adv7511->i2c_edid) {
ret = -ENOMEM;
ret = -EINVAL;
goto uninit_regulators;
}
regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR,
adv7511->i2c_edid->addr << 1);
adv7511->i2c_packet = i2c_new_secondary_device(i2c, "packet",
ADV7511_PACKET_I2C_ADDR_DEFAULT);
if (!adv7511->i2c_packet) {
ret = -EINVAL;
goto err_i2c_unregister_edid;
}
regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR,
adv7511->i2c_packet->addr << 1);
ret = adv7511_init_cec_regmap(adv7511);
if (ret)
goto err_i2c_unregister_edid;
goto err_i2c_unregister_packet;
regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR,
adv7511->i2c_cec->addr << 1);
INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work);
@@ -1207,6 +1216,8 @@ err_unregister_cec:
i2c_unregister_device(adv7511->i2c_cec);
if (adv7511->cec_clk)
clk_disable_unprepare(adv7511->cec_clk);
err_i2c_unregister_packet:
i2c_unregister_device(adv7511->i2c_packet);
err_i2c_unregister_edid:
i2c_unregister_device(adv7511->i2c_edid);
uninit_regulators:
@@ -1233,6 +1244,7 @@ static int adv7511_remove(struct i2c_client *i2c)
cec_unregister_adapter(adv7511->cec_adap);
i2c_unregister_device(adv7511->i2c_packet);
i2c_unregister_device(adv7511->i2c_edid);
return 0;

333
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
View File

@@ -43,8 +43,10 @@ struct bridge_init {
struct device_node *node;
};
static void analogix_dp_init_dp(struct analogix_dp_device *dp)
static int analogix_dp_init_dp(struct analogix_dp_device *dp)
{
int ret;
analogix_dp_reset(dp);
analogix_dp_swreset(dp);
@@ -56,10 +58,13 @@ static void analogix_dp_init_dp(struct analogix_dp_device *dp)
analogix_dp_enable_sw_function(dp);
analogix_dp_config_interrupt(dp);
analogix_dp_init_analog_func(dp);
ret = analogix_dp_init_analog_func(dp);
if (ret)
return ret;
analogix_dp_init_hpd(dp);
analogix_dp_init_aux(dp);
return 0;
}
static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
@@ -71,7 +76,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
return 0;
timeout_loop++;
usleep_range(10, 11);
usleep_range(1000, 1100);
}
/*
@@ -148,87 +153,146 @@ int analogix_dp_disable_psr(struct analogix_dp_device *dp)
psr_vsc.DB1 = 0;
ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
if (ret != 1)
if (ret != 1) {
dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
return ret;
}
return analogix_dp_send_psr_spd(dp, &psr_vsc, false);
}
EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
{
unsigned char psr_version;
int ret;
ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
if (ret != 1) {
dev_err(dp->dev, "failed to get PSR version, disable it\n");
return ret;
}
drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
return 0;
}
static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
{
unsigned char psr_en;
int ret;
/* Disable psr function */
drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
if (ret != 1) {
dev_err(dp->dev, "failed to get psr config\n");
goto end;
}
psr_en &= ~DP_PSR_ENABLE;
drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
if (ret != 1) {
dev_err(dp->dev, "failed to disable panel psr\n");
goto end;
}
/* Main-Link transmitter remains active during PSR active states */
psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
if (ret != 1) {
dev_err(dp->dev, "failed to set panel psr\n");
goto end;
}
/* Enable psr function */
psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
DP_PSR_CRC_VERIFICATION;
drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
if (ret != 1) {
dev_err(dp->dev, "failed to set panel psr\n");
goto end;
}
analogix_dp_enable_psr_crc(dp);
return 0;
end:
dev_err(dp->dev, "enable psr fail, force to disable psr\n");
dp->psr_enable = false;
return ret;
}
static void
static int
analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
bool enable)
{
u8 data;
int ret;
drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
if (ret != 1)
return ret;
if (enable)
drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
DP_LANE_COUNT_ENHANCED_FRAME_EN |
DPCD_LANE_COUNT_SET(data));
ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
DP_LANE_COUNT_ENHANCED_FRAME_EN |
DPCD_LANE_COUNT_SET(data));
else
drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
DPCD_LANE_COUNT_SET(data));
ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
DPCD_LANE_COUNT_SET(data));
return ret < 0 ? ret : 0;
}
static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
u8 *enhanced_mode_support)
{
u8 data;
int retval;
int ret;
drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
retval = DPCD_ENHANCED_FRAME_CAP(data);
ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
if (ret != 1) {
*enhanced_mode_support = 0;
return ret;
}
return retval;
*enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
return 0;
}
static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
{
u8 data;
int ret;
ret = analogix_dp_is_enhanced_mode_available(dp, &data);
if (ret < 0)
return ret;
ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
if (ret < 0)
return ret;
data = analogix_dp_is_enhanced_mode_available(dp);
analogix_dp_enable_rx_to_enhanced_mode(dp, data);
analogix_dp_enable_enhanced_mode(dp, data);
return 0;
}
static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
{
int ret;
analogix_dp_set_training_pattern(dp, DP_NONE);
drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
DP_TRAINING_PATTERN_DISABLE);
ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
DP_TRAINING_PATTERN_DISABLE);
return ret < 0 ? ret : 0;
}
static void
@@ -276,6 +340,12 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
if (retval < 0)
return retval;
/* set enhanced mode if available */
retval = analogix_dp_set_enhanced_mode(dp);
if (retval < 0) {
dev_err(dp->dev, "failed to set enhance mode\n");
return retval;
}
/* Set TX pre-emphasis to minimum */
for (lane = 0; lane < lane_count; lane++)
@@ -531,7 +601,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
{
int lane, lane_count, retval;
u32 reg;
u8 link_align, link_status[2], adjust_request[2], spread;
u8 link_align, link_status[2], adjust_request[2];
usleep_range(400, 401);
@@ -560,10 +630,11 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
/* traing pattern Set to Normal */
analogix_dp_training_pattern_dis(dp);
retval = analogix_dp_training_pattern_dis(dp);
if (retval < 0)
return retval;
dev_info(dp->dev, "Link Training success!\n");
analogix_dp_get_link_bandwidth(dp, &reg);
dp->link_train.link_rate = reg;
dev_dbg(dp->dev, "final bandwidth = %.2x\n",
@@ -574,22 +645,6 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
dev_dbg(dp->dev, "final lane count = %.2x\n",
dp->link_train.lane_count);
retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD,
&spread);
if (retval != 1) {
dev_err(dp->dev, "failed to read downspread %d\n",
retval);
dp->fast_train_support = false;
} else {
dp->fast_train_support =
(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ?
true : false;
}
dev_dbg(dp->dev, "fast link training %s\n",
dp->fast_train_support ? "supported" : "unsupported");
/* set enhanced mode if available */
analogix_dp_set_enhanced_mode(dp);
dp->link_train.lt_state = FINISHED;
return 0;
@@ -793,7 +848,7 @@ static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
static int analogix_dp_train_link(struct analogix_dp_device *dp)
{
if (dp->fast_train_support)
if (dp->fast_train_enable)
return analogix_dp_fast_link_train(dp);
return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
@@ -819,11 +874,10 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
break;
if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Timeout of video streamclk ok\n");
dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
return -ETIMEDOUT;
}
usleep_range(1, 2);
usleep_range(1000, 1001);
}
/* Set to use the register calculated M/N video */
@@ -838,6 +892,9 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
/* Configure video slave mode */
analogix_dp_enable_video_master(dp, 0);
/* Enable video */
analogix_dp_start_video(dp);
timeout_loop = 0;
for (;;) {
@@ -850,8 +907,9 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
done_count = 0;
}
if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Timeout of video streamclk ok\n");
return -ETIMEDOUT;
dev_warn(dp->dev,
"Ignoring timeout of video streamclk ok\n");
break;
}
usleep_range(1000, 1001);
@@ -860,24 +918,32 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
return 0;
}
static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
bool enable)
static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
bool enable)
{
u8 data;
int ret;
if (enable) {
analogix_dp_enable_scrambling(dp);
drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
&data);
if (ret != 1)
return ret;
ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
} else {
analogix_dp_disable_scrambling(dp);
drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
&data);
if (ret != 1)
return ret;
ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
}
return ret < 0 ? ret : 0;
}
static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
@@ -916,7 +982,23 @@ static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
return IRQ_HANDLED;
}
static void analogix_dp_commit(struct analogix_dp_device *dp)
static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
{
int ret;
u8 spread;
ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
if (ret != 1) {
dev_err(dp->dev, "failed to read downspread %d\n", ret);
return ret;
}
dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
dev_dbg(dp->dev, "fast link training %s\n",
dp->fast_train_enable ? "supported" : "unsupported");
return 0;
}
static int analogix_dp_commit(struct analogix_dp_device *dp)
{
int ret;
@@ -926,34 +1008,50 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
DRM_ERROR("failed to disable the panel\n");
}
ret = readx_poll_timeout(analogix_dp_train_link, dp, ret, !ret, 100,
DP_TIMEOUT_TRAINING_US * 5);
ret = analogix_dp_train_link(dp);
if (ret) {
dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
return;
return ret;
}
analogix_dp_enable_scramble(dp, 1);
analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
analogix_dp_enable_enhanced_mode(dp, 1);
ret = analogix_dp_enable_scramble(dp, 1);
if (ret < 0) {
dev_err(dp->dev, "can not enable scramble\n");
return ret;
}
analogix_dp_init_video(dp);
ret = analogix_dp_config_video(dp);
if (ret)
if (ret) {
dev_err(dp->dev, "unable to config video\n");
return ret;
}
/* Safe to enable the panel now */
if (dp->plat_data->panel) {
if (drm_panel_enable(dp->plat_data->panel))
ret = drm_panel_enable(dp->plat_data->panel);
if (ret) {
DRM_ERROR("failed to enable the panel\n");
return ret;
}
}
/* Enable video */
analogix_dp_start_video(dp);
ret = analogix_dp_detect_sink_psr(dp);
if (ret)
return ret;
dp->psr_enable = analogix_dp_detect_sink_psr(dp);
if (dp->psr_enable)
analogix_dp_enable_sink_psr(dp);
if (dp->psr_enable) {
ret = analogix_dp_enable_sink_psr(dp);
if (ret)
return ret;
}
/* Check whether panel supports fast training */
ret = analogix_dp_fast_link_train_detection(dp);
if (ret)
dp->psr_enable = false;
return ret;
}
/*
@@ -1150,24 +1248,80 @@ static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
DRM_ERROR("failed to setup the panel ret = %d\n", ret);
}
static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
{
int ret;
pm_runtime_get_sync(dp->dev);
ret = clk_prepare_enable(dp->clock);
if (ret < 0) {
DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
goto out_dp_clk_pre;
}
if (dp->plat_data->power_on_start)
dp->plat_data->power_on_start(dp->plat_data);
phy_power_on(dp->phy);
ret = analogix_dp_init_dp(dp);
if (ret)
goto out_dp_init;
/*
* According to DP spec v1.3 chap 3.5.1.2 Link Training,
* We should first make sure the HPD signal is asserted high by device
* when we want to establish a link with it.
*/
ret = analogix_dp_detect_hpd(dp);
if (ret) {
DRM_ERROR("failed to get hpd single ret = %d\n", ret);
goto out_dp_init;
}
ret = analogix_dp_commit(dp);
if (ret) {
DRM_ERROR("dp commit error, ret = %d\n", ret);
goto out_dp_init;
}
if (dp->plat_data->power_on_end)
dp->plat_data->power_on_end(dp->plat_data);
enable_irq(dp->irq);
return 0;
out_dp_init:
phy_power_off(dp->phy);
if (dp->plat_data->power_off)
dp->plat_data->power_off(dp->plat_data);
clk_disable_unprepare(dp->clock);
out_dp_clk_pre:
pm_runtime_put_sync(dp->dev);
return ret;
}
static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
{
struct analogix_dp_device *dp = bridge->driver_private;
int timeout_loop = 0;
if (dp->dpms_mode == DRM_MODE_DPMS_ON)
return;
pm_runtime_get_sync(dp->dev);
if (dp->plat_data->power_on)
dp->plat_data->power_on(dp->plat_data);
phy_power_on(dp->phy);
analogix_dp_init_dp(dp);
enable_irq(dp->irq);
analogix_dp_commit(dp);
dp->dpms_mode = DRM_MODE_DPMS_ON;
while (timeout_loop < MAX_PLL_LOCK_LOOP) {
if (analogix_dp_set_bridge(dp) == 0) {
dp->dpms_mode = DRM_MODE_DPMS_ON;
return;
}
dev_err(dp->dev, "failed to set bridge, retry: %d\n",
timeout_loop);
timeout_loop++;
usleep_range(10, 11);
}
dev_err(dp->dev, "too many times retry set bridge, give it up\n");
}
static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
@@ -1186,11 +1340,15 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
}
disable_irq(dp->irq);
phy_power_off(dp->phy);
if (dp->plat_data->power_off)
dp->plat_data->power_off(dp->plat_data);
analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
phy_power_off(dp->phy);
clk_disable_unprepare(dp->clock);
pm_runtime_put_sync(dp->dev);
ret = analogix_dp_prepare_panel(dp, false, true);
@@ -1198,6 +1356,7 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
DRM_ERROR("failed to setup the panel ret = %d\n", ret);
dp->psr_enable = false;
dp->fast_train_enable = false;
dp->dpms_mode = DRM_MODE_DPMS_OFF;
}

5
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
View File

@@ -19,6 +19,7 @@
#define DP_TIMEOUT_LOOP_COUNT 100
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
#define MAX_PLL_LOCK_LOOP 5
/* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
#define DP_TIMEOUT_TRAINING_US 22000
@@ -173,7 +174,7 @@ struct analogix_dp_device {
int hpd_gpio;
bool force_hpd;
bool psr_enable;
bool fast_train_support;
bool fast_train_enable;
struct mutex panel_lock;
bool panel_is_modeset;
@@ -197,7 +198,7 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
enum analog_power_block block,
bool enable);
void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
int analogix_dp_init_analog_func(struct analogix_dp_device *dp);
void analogix_dp_init_hpd(struct analogix_dp_device *dp);
void analogix_dp_force_hpd(struct analogix_dp_device *dp);
enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);

236
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
View File

@@ -126,9 +126,14 @@ void analogix_dp_reset(struct analogix_dp_device *dp)
analogix_dp_stop_video(dp);
analogix_dp_enable_video_mute(dp, 0);
reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
HDCP_FUNC_EN_N | SW_FUNC_EN_N;
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
reg = RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N |
SW_FUNC_EN_N;
else
reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
HDCP_FUNC_EN_N | SW_FUNC_EN_N;
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
@@ -230,16 +235,20 @@ enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
{
u32 reg;
u32 mask = DP_PLL_PD;
u32 pd_addr = ANALOGIX_DP_PLL_CTL;
if (enable) {
reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
reg |= DP_PLL_PD;
writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
} else {
reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
reg &= ~DP_PLL_PD;
writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
pd_addr = ANALOGIX_DP_PD;
mask = RK_PLL_PD;
}
reg = readl(dp->reg_base + pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + pd_addr);
}
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
@@ -248,83 +257,98 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
{
u32 reg;
u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
u32 mask;
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
phy_pd_addr = ANALOGIX_DP_PD;
switch (block) {
case AUX_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= AUX_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~AUX_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
mask = RK_AUX_PD;
else
mask = AUX_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH0_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH0_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH0_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH0_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH1_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH1_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH1_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH1_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH2_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH2_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH2_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH2_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH3_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH3_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH3_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH3_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case ANALOG_TOTAL:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= DP_PHY_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~DP_PHY_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
/*
* There is no bit named DP_PHY_PD, so We used DP_INC_BG
* to power off everything instead of DP_PHY_PD in
* Rockchip
*/
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
mask = DP_INC_BG;
else
mask = DP_PHY_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
usleep_range(10, 15);
break;
case POWER_ALL:
if (enable) {
reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
CH1_PD | CH0_PD;
reg = DP_ALL_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = DP_ALL_PD;
writel(reg, dp->reg_base + phy_pd_addr);
usleep_range(10, 15);
reg &= ~DP_INC_BG;
writel(reg, dp->reg_base + phy_pd_addr);
usleep_range(10, 15);
writel(0x00, dp->reg_base + phy_pd_addr);
}
break;
@@ -333,7 +357,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
}
}
void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
{
u32 reg;
int timeout_loop = 0;
@@ -355,7 +379,7 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "failed to get pll lock status\n");
return;
return -ETIMEDOUT;
}
usleep_range(10, 20);
}
@@ -366,6 +390,7 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
| AUX_FUNC_EN_N);
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
return 0;
}
void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
@@ -450,17 +475,22 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
reg = RPLY_RECEIV | AUX_ERR;
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
analogix_dp_set_analog_power_down(dp, AUX_BLOCK, true);
usleep_range(10, 11);
analogix_dp_set_analog_power_down(dp, AUX_BLOCK, false);
analogix_dp_reset_aux(dp);
/* Disable AUX transaction H/W retry */
/* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
AUX_HW_RETRY_COUNT_SEL(3) |
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
reg = 0;
else
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
AUX_HW_RETRY_COUNT_SEL(0) |
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3);
/* Disable AUX transaction H/W retry */
reg |= AUX_HW_RETRY_COUNT_SEL(0) |
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -947,8 +977,12 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
u32 reg;
reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
reg |= MASTER_VID_FUNC_EN_N;
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
reg &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
} else {
reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
reg |= MASTER_VID_FUNC_EN_N;
}
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
@@ -1072,10 +1106,11 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
struct drm_dp_aux_msg *msg)
{
u32 reg;
u32 status_reg;
u8 *buffer = msg->buffer;
int timeout_loop = 0;
unsigned int i;
int num_transferred = 0;
int ret;
/* Buffer size of AUX CH is 16 bytes */
if (WARN_ON(msg->size > 16))
@@ -1139,17 +1174,20 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
/* Is AUX CH command reply received? */
ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2,
reg, !(reg & AUX_EN), 25, 500 * 1000);
if (ret) {
dev_err(dp->dev, "AUX CH enable timeout!\n");
goto aux_error;
}
/* TODO: Wait for an interrupt instead of looping? */
reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
while (!(reg & RPLY_RECEIV)) {
timeout_loop++;
if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "AUX CH command reply failed!\n");
return -ETIMEDOUT;
}
reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
usleep_range(10, 11);
/* Is AUX CH command reply received? */
ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA,
reg, reg & RPLY_RECEIV, 10, 20 * 1000);
if (ret) {
dev_err(dp->dev, "AUX CH cmd reply timeout!\n");
goto aux_error;
}
/* Clear interrupt source for AUX CH command reply */
@@ -1157,17 +1195,13 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
/* Clear interrupt source for AUX CH access error */
reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
if (reg & AUX_ERR) {
status_reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
if ((reg & AUX_ERR) || (status_reg & AUX_STATUS_MASK)) {
writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
return -EREMOTEIO;
}
/* Check AUX CH error access status */
reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
if ((reg & AUX_STATUS_MASK)) {
dev_err(dp->dev, "AUX CH error happened: %d\n\n",
reg & AUX_STATUS_MASK);
return -EREMOTEIO;
dev_warn(dp->dev, "AUX CH error happened: %#x (%d)\n",
status_reg & AUX_STATUS_MASK, !!(reg & AUX_ERR));
goto aux_error;
}
if (msg->request & DP_AUX_I2C_READ) {
@@ -1193,4 +1227,10 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
msg->reply = DP_AUX_NATIVE_REPLY_ACK;
return num_transferred > 0 ? num_transferred : -EBUSY;
aux_error:
/* if aux err happen, reset aux */
analogix_dp_init_aux(dp);
return -EREMOTEIO;
}

7
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
View File

@@ -127,7 +127,9 @@
/* ANALOGIX_DP_FUNC_EN_1 */
#define MASTER_VID_FUNC_EN_N (0x1 << 7)
#define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
#define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
#define AUD_FUNC_EN_N (0x1 << 3)
#define HDCP_FUNC_EN_N (0x1 << 2)
@@ -342,12 +344,17 @@
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
/* ANALOGIX_DP_PHY_PD */
#define DP_INC_BG (0x1 << 7)
#define DP_EXP_BG (0x1 << 6)
#define DP_PHY_PD (0x1 << 5)
#define RK_AUX_PD (0x1 << 5)
#define AUX_PD (0x1 << 4)
#define RK_PLL_PD (0x1 << 4)
#define CH3_PD (0x1 << 3)
#define CH2_PD (0x1 << 2)
#define CH1_PD (0x1 << 1)
#define CH0_PD (0x1 << 0)
#define DP_ALL_PD (0xff)
/* ANALOGIX_DP_PHY_TEST */
#define MACRO_RST (0x1 << 5)

1623
drivers/gpu/drm/bridge/cdns-dsi.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
View File

@@ -152,7 +152,6 @@ static struct platform_driver snd_dw_hdmi_driver = {
.remove = snd_dw_hdmi_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
},
};
module_platform_driver(snd_dw_hdmi_driver);

18
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
View File

@@ -1,12 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
* Copyright (C) STMicroelectronics SA 2017
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Modified by Philippe Cornu <philippe.cornu@st.com>
* This generic Synopsys DesignWare MIPI DSI host driver is based on the
* Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
@@ -775,20 +771,20 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
clk_prepare_enable(dsi->pclk);
ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
dsi->lanes, dsi->format, &dsi->lane_mbps);
if (ret)
DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
pm_runtime_get_sync(dsi->dev);
dw_mipi_dsi_init(dsi);
dw_mipi_dsi_dpi_config(dsi, mode);
dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
dw_mipi_dsi_packet_handler_config(dsi);
dw_mipi_dsi_video_mode_config(dsi);
dw_mipi_dsi_video_packet_config(dsi, mode);
dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
dw_mipi_dsi_command_mode_config(dsi);
dw_mipi_dsi_line_timer_config(dsi, mode);
dw_mipi_dsi_vertical_timing_config(dsi, mode);
dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
dw_mipi_dsi_dphy_init(dsi);
dw_mipi_dsi_dphy_timing_config(dsi);
@@ -802,7 +798,7 @@ static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
dw_mipi_dsi_dphy_enable(dsi);
dw_mipi_dsi_wait_for_two_frames(mode);
dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
dw_mipi_dsi_set_mode(dsi, 0);

2
drivers/gpu/drm/bridge/tc358767.c
View File

@@ -1102,7 +1102,7 @@ static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
return true;
}
static int tc_connector_mode_valid(struct drm_connector *connector,
static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
/* DPI interface clock limitation: upto 154 MHz */

206
drivers/gpu/drm/bridge/thc63lvd1024.c Normal file
View File

@@ -0,0 +1,206 @@
// SPDX-License-Identifier: GPL-2.0
/*
* THC63LVD1024 LVDS to parallel data DRM bridge driver.
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
*/
#include <drm/drmP.h>
#include <drm/drm_bridge.h>
#include <drm/drm_panel.h>
#include <linux/gpio/consumer.h>
#include <linux/of_graph.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
enum thc63_ports {
THC63_LVDS_IN0,
THC63_LVDS_IN1,
THC63_RGB_OUT0,
THC63_RGB_OUT1,
};
struct thc63_dev {
struct device *dev;
struct regulator *vcc;
struct gpio_desc *pdwn;
struct gpio_desc *oe;
struct drm_bridge bridge;
struct drm_bridge *next;
};
static inline struct thc63_dev *to_thc63(struct drm_bridge *bridge)
{
return container_of(bridge, struct thc63_dev, bridge);
}
static int thc63_attach(struct drm_bridge *bridge)
{
struct thc63_dev *thc63 = to_thc63(bridge);
return drm_bridge_attach(bridge->encoder, thc63->next, bridge);
}
static void thc63_enable(struct drm_bridge *bridge)
{
struct thc63_dev *thc63 = to_thc63(bridge);
int ret;
ret = regulator_enable(thc63->vcc);
if (ret) {
dev_err(thc63->dev,
"Failed to enable regulator \"vcc\": %d\n", ret);
return;
}
gpiod_set_value(thc63->pdwn, 0);
gpiod_set_value(thc63->oe, 1);
}
static void thc63_disable(struct drm_bridge *bridge)
{
struct thc63_dev *thc63 = to_thc63(bridge);
int ret;
gpiod_set_value(thc63->oe, 0);
gpiod_set_value(thc63->pdwn, 1);
ret = regulator_disable(thc63->vcc);
if (ret)
dev_err(thc63->dev,
"Failed to disable regulator \"vcc\": %d\n", ret);
}
static const struct drm_bridge_funcs thc63_bridge_func = {
.attach = thc63_attach,
.enable = thc63_enable,
.disable = thc63_disable,
};
static int thc63_parse_dt(struct thc63_dev *thc63)
{
struct device_node *thc63_out;
struct device_node *remote;
thc63_out = of_graph_get_endpoint_by_regs(thc63->dev->of_node,
THC63_RGB_OUT0, -1);
if (!thc63_out) {
dev_err(thc63->dev, "Missing endpoint in port@%u\n",
THC63_RGB_OUT0);
return -ENODEV;
}
remote = of_graph_get_remote_port_parent(thc63_out);
of_node_put(thc63_out);
if (!remote) {
dev_err(thc63->dev, "Endpoint in port@%u unconnected\n",
THC63_RGB_OUT0);
return -ENODEV;
}
if (!of_device_is_available(remote)) {
dev_err(thc63->dev, "port@%u remote endpoint is disabled\n",
THC63_RGB_OUT0);
of_node_put(remote);
return -ENODEV;
}
thc63->next = of_drm_find_bridge(remote);
of_node_put(remote);
if (!thc63->next)
return -EPROBE_DEFER;
return 0;
}
static int thc63_gpio_init(struct thc63_dev *thc63)
{
thc63->oe = devm_gpiod_get_optional(thc63->dev, "oe", GPIOD_OUT_LOW);
if (IS_ERR(thc63->oe)) {
dev_err(thc63->dev, "Unable to get \"oe-gpios\": %ld\n",
PTR_ERR(thc63->oe));
return PTR_ERR(thc63->oe);
}
thc63->pdwn = devm_gpiod_get_optional(thc63->dev, "powerdown",
GPIOD_OUT_HIGH);
if (IS_ERR(thc63->pdwn)) {
dev_err(thc63->dev, "Unable to get \"powerdown-gpios\": %ld\n",
PTR_ERR(thc63->pdwn));
return PTR_ERR(thc63->pdwn);
}
return 0;
}
static int thc63_probe(struct platform_device *pdev)
{
struct thc63_dev *thc63;
int ret;
thc63 = devm_kzalloc(&pdev->dev, sizeof(*thc63), GFP_KERNEL);
if (!thc63)
return -ENOMEM;
thc63->dev = &pdev->dev;
platform_set_drvdata(pdev, thc63);
thc63->vcc = devm_regulator_get_optional(thc63->dev, "vcc");
if (IS_ERR(thc63->vcc)) {
if (PTR_ERR(thc63->vcc) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_err(thc63->dev, "Unable to get \"vcc\" supply: %ld\n",
PTR_ERR(thc63->vcc));
return PTR_ERR(thc63->vcc);
}
ret = thc63_gpio_init(thc63);
if (ret)
return ret;
ret = thc63_parse_dt(thc63);
if (ret)
return ret;
thc63->bridge.driver_private = thc63;
thc63->bridge.of_node = pdev->dev.of_node;
thc63->bridge.funcs = &thc63_bridge_func;
drm_bridge_add(&thc63->bridge);
return 0;
}
static int thc63_remove(struct platform_device *pdev)
{
struct thc63_dev *thc63 = platform_get_drvdata(pdev);
drm_bridge_remove(&thc63->bridge);
return 0;
}
static const struct of_device_id thc63_match[] = {
{ .compatible = "thine,thc63lvd1024", },
{ },
};
MODULE_DEVICE_TABLE(of, thc63_match);
static struct platform_driver thc63_driver = {
.probe = thc63_probe,
.remove = thc63_remove,
.driver = {
.name = "thc63lvd1024",
.of_match_table = thc63_match,
},
};
module_platform_driver(thc63_driver);
MODULE_AUTHOR("Jacopo Mondi <jacopo@jmondi.org>");
MODULE_DESCRIPTION("Thine THC63LVD1024 LVDS decoder DRM bridge driver");
MODULE_LICENSE("GPL v2");