media: staging/intel-ipu3: css: Add support for firmware management
Introduce functions to load and install ImgU FW blobs. Signed-off-by: Yong Zhi <yong.zhi@intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:

committed by
Mauro Carvalho Chehab

parent
e9fad6f1d2
commit
09d290f0ba
264
drivers/staging/media/ipu3/ipu3-css-fw.c
Normal file
264
drivers/staging/media/ipu3/ipu3-css-fw.c
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@@ -0,0 +1,264 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Intel Corporation
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#include <linux/device.h>
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#include <linux/firmware.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include "ipu3-css.h"
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#include "ipu3-css-fw.h"
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#include "ipu3-dmamap.h"
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static void ipu3_css_fw_show_binary(struct device *dev, struct imgu_fw_info *bi,
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const char *name)
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{
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unsigned int i;
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dev_dbg(dev, "found firmware binary type %i size %i name %s\n",
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bi->type, bi->blob.size, name);
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if (bi->type != IMGU_FW_ISP_FIRMWARE)
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return;
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dev_dbg(dev, " id %i mode %i bds 0x%x veceven %i/%i out_pins %i\n",
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bi->info.isp.sp.id, bi->info.isp.sp.pipeline.mode,
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bi->info.isp.sp.bds.supported_bds_factors,
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bi->info.isp.sp.enable.vf_veceven,
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bi->info.isp.sp.vf_dec.is_variable,
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bi->info.isp.num_output_pins);
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dev_dbg(dev, " input (%i,%i)-(%i,%i) formats %s%s%s\n",
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bi->info.isp.sp.input.min_width,
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bi->info.isp.sp.input.min_height,
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bi->info.isp.sp.input.max_width,
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bi->info.isp.sp.input.max_height,
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bi->info.isp.sp.enable.input_yuv ? "yuv420 " : "",
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bi->info.isp.sp.enable.input_feeder ||
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bi->info.isp.sp.enable.input_raw ? "raw8 raw10 " : "",
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bi->info.isp.sp.enable.input_raw ? "raw12" : "");
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dev_dbg(dev, " internal (%i,%i)\n",
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bi->info.isp.sp.internal.max_width,
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bi->info.isp.sp.internal.max_height);
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dev_dbg(dev, " output (%i,%i)-(%i,%i) formats",
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bi->info.isp.sp.output.min_width,
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bi->info.isp.sp.output.min_height,
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bi->info.isp.sp.output.max_width,
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bi->info.isp.sp.output.max_height);
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for (i = 0; i < bi->info.isp.num_output_formats; i++)
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dev_dbg(dev, " %i", bi->info.isp.output_formats[i]);
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dev_dbg(dev, " vf");
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for (i = 0; i < bi->info.isp.num_vf_formats; i++)
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dev_dbg(dev, " %i", bi->info.isp.vf_formats[i]);
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dev_dbg(dev, "\n");
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}
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unsigned int ipu3_css_fw_obgrid_size(const struct imgu_fw_info *bi)
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{
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unsigned int width = DIV_ROUND_UP(bi->info.isp.sp.internal.max_width,
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IMGU_OBGRID_TILE_SIZE * 2) + 1;
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unsigned int height = DIV_ROUND_UP(bi->info.isp.sp.internal.max_height,
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IMGU_OBGRID_TILE_SIZE * 2) + 1;
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unsigned int obgrid_size;
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width = ALIGN(width, IPU3_UAPI_ISP_VEC_ELEMS / 4);
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obgrid_size = PAGE_ALIGN(width * height *
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sizeof(struct ipu3_uapi_obgrid_param)) *
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bi->info.isp.sp.iterator.num_stripes;
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return obgrid_size;
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}
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void *ipu3_css_fw_pipeline_params(struct ipu3_css *css,
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enum imgu_abi_param_class c,
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enum imgu_abi_memories m,
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struct imgu_fw_isp_parameter *par,
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size_t par_size, void *binary_params)
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{
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struct imgu_fw_info *bi = &css->fwp->binary_header[css->current_binary];
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if (par->offset + par->size >
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bi->info.isp.sp.mem_initializers.params[c][m].size)
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return NULL;
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if (par->size != par_size)
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pr_warn("parameter size doesn't match defined size\n");
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if (par->size < par_size)
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return NULL;
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return binary_params + par->offset;
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}
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void ipu3_css_fw_cleanup(struct ipu3_css *css)
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{
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struct imgu_device *imgu = dev_get_drvdata(css->dev);
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if (css->binary) {
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unsigned int i;
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for (i = 0; i < css->fwp->file_header.binary_nr; i++)
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ipu3_dmamap_free(imgu, &css->binary[i]);
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kfree(css->binary);
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}
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if (css->fw)
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release_firmware(css->fw);
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css->binary = NULL;
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css->fw = NULL;
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}
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int ipu3_css_fw_init(struct ipu3_css *css)
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{
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static const u32 BLOCK_MAX = 65536;
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struct imgu_device *imgu = dev_get_drvdata(css->dev);
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struct device *dev = css->dev;
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unsigned int i, j, binary_nr;
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int r;
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r = request_firmware(&css->fw, IMGU_FW_NAME, css->dev);
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if (r)
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return r;
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/* Check and display fw header info */
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css->fwp = (struct imgu_fw_header *)css->fw->data;
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if (css->fw->size < sizeof(struct imgu_fw_header *) ||
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css->fwp->file_header.h_size != sizeof(struct imgu_fw_bi_file_h))
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goto bad_fw;
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if (sizeof(struct imgu_fw_bi_file_h) +
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css->fwp->file_header.binary_nr * sizeof(struct imgu_fw_info) >
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css->fw->size)
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goto bad_fw;
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dev_info(dev, "loaded firmware version %.64s, %u binaries, %zu bytes\n",
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css->fwp->file_header.version, css->fwp->file_header.binary_nr,
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css->fw->size);
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/* Validate and display info on fw binaries */
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binary_nr = css->fwp->file_header.binary_nr;
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css->fw_bl = -1;
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css->fw_sp[0] = -1;
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css->fw_sp[1] = -1;
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for (i = 0; i < binary_nr; i++) {
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struct imgu_fw_info *bi = &css->fwp->binary_header[i];
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const char *name = (void *)css->fwp + bi->blob.prog_name_offset;
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size_t len;
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if (bi->blob.prog_name_offset >= css->fw->size)
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goto bad_fw;
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len = strnlen(name, css->fw->size - bi->blob.prog_name_offset);
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if (len + 1 > css->fw->size - bi->blob.prog_name_offset ||
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len + 1 >= IMGU_ABI_MAX_BINARY_NAME)
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goto bad_fw;
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if (bi->blob.size != bi->blob.text_size + bi->blob.icache_size
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+ bi->blob.data_size + bi->blob.padding_size)
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goto bad_fw;
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if (bi->blob.offset + bi->blob.size > css->fw->size)
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goto bad_fw;
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if (bi->type == IMGU_FW_BOOTLOADER_FIRMWARE) {
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css->fw_bl = i;
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if (bi->info.bl.sw_state >= css->iomem_length ||
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bi->info.bl.num_dma_cmds >= css->iomem_length ||
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bi->info.bl.dma_cmd_list >= css->iomem_length)
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goto bad_fw;
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}
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if (bi->type == IMGU_FW_SP_FIRMWARE ||
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bi->type == IMGU_FW_SP1_FIRMWARE) {
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css->fw_sp[bi->type == IMGU_FW_SP_FIRMWARE ? 0 : 1] = i;
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if (bi->info.sp.per_frame_data >= css->iomem_length ||
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bi->info.sp.init_dmem_data >= css->iomem_length ||
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bi->info.sp.host_sp_queue >= css->iomem_length ||
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bi->info.sp.isp_started >= css->iomem_length ||
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bi->info.sp.sw_state >= css->iomem_length ||
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bi->info.sp.sleep_mode >= css->iomem_length ||
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bi->info.sp.invalidate_tlb >= css->iomem_length ||
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bi->info.sp.host_sp_com >= css->iomem_length ||
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bi->info.sp.output + 12 >= css->iomem_length ||
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bi->info.sp.host_sp_queues_initialized >=
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css->iomem_length)
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goto bad_fw;
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}
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if (bi->type != IMGU_FW_ISP_FIRMWARE)
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continue;
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if (bi->info.isp.sp.pipeline.mode >= IPU3_CSS_PIPE_ID_NUM)
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goto bad_fw;
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if (bi->info.isp.sp.iterator.num_stripes >
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IPU3_UAPI_MAX_STRIPES)
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goto bad_fw;
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if (bi->info.isp.num_vf_formats > IMGU_ABI_FRAME_FORMAT_NUM ||
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bi->info.isp.num_output_formats > IMGU_ABI_FRAME_FORMAT_NUM)
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goto bad_fw;
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for (j = 0; j < bi->info.isp.num_output_formats; j++)
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if (bi->info.isp.output_formats[j] < 0 ||
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bi->info.isp.output_formats[j] >=
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IMGU_ABI_FRAME_FORMAT_NUM)
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goto bad_fw;
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for (j = 0; j < bi->info.isp.num_vf_formats; j++)
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if (bi->info.isp.vf_formats[j] < 0 ||
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bi->info.isp.vf_formats[j] >=
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IMGU_ABI_FRAME_FORMAT_NUM)
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goto bad_fw;
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if (bi->info.isp.sp.block.block_width <= 0 ||
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bi->info.isp.sp.block.block_width > BLOCK_MAX ||
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bi->info.isp.sp.block.output_block_height <= 0 ||
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bi->info.isp.sp.block.output_block_height > BLOCK_MAX)
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goto bad_fw;
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if (bi->blob.memory_offsets.offsets[IMGU_ABI_PARAM_CLASS_PARAM]
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+ sizeof(struct imgu_fw_param_memory_offsets) >
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css->fw->size ||
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bi->blob.memory_offsets.offsets[IMGU_ABI_PARAM_CLASS_CONFIG]
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+ sizeof(struct imgu_fw_config_memory_offsets) >
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css->fw->size ||
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bi->blob.memory_offsets.offsets[IMGU_ABI_PARAM_CLASS_STATE]
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+ sizeof(struct imgu_fw_state_memory_offsets) >
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css->fw->size)
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goto bad_fw;
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ipu3_css_fw_show_binary(dev, bi, name);
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}
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if (css->fw_bl == -1 || css->fw_sp[0] == -1 || css->fw_sp[1] == -1)
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goto bad_fw;
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/* Allocate and map fw binaries into IMGU */
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css->binary = kcalloc(binary_nr, sizeof(*css->binary), GFP_KERNEL);
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if (!css->binary) {
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r = -ENOMEM;
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goto error_out;
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}
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for (i = 0; i < css->fwp->file_header.binary_nr; i++) {
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struct imgu_fw_info *bi = &css->fwp->binary_header[i];
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void *blob = (void *)css->fwp + bi->blob.offset;
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size_t size = bi->blob.size;
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if (!ipu3_dmamap_alloc(imgu, &css->binary[i], size)) {
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r = -ENOMEM;
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goto error_out;
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}
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memcpy(css->binary[i].vaddr, blob, size);
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}
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return 0;
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bad_fw:
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dev_err(dev, "invalid firmware binary, size %u\n", (int)css->fw->size);
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r = -ENODEV;
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error_out:
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ipu3_css_fw_cleanup(css);
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return r;
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}
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188
drivers/staging/media/ipu3/ipu3-css-fw.h
Normal file
188
drivers/staging/media/ipu3/ipu3-css-fw.h
Normal file
@@ -0,0 +1,188 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2018 Intel Corporation */
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#ifndef __IPU3_CSS_FW_H
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#define __IPU3_CSS_FW_H
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/******************* Firmware file definitions *******************/
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#define IMGU_FW_NAME "ipu3-fw.bin"
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typedef u32 imgu_fw_ptr;
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enum imgu_fw_type {
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IMGU_FW_SP_FIRMWARE, /* Firmware for the SP */
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IMGU_FW_SP1_FIRMWARE, /* Firmware for the SP1 */
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IMGU_FW_ISP_FIRMWARE, /* Firmware for the ISP */
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IMGU_FW_BOOTLOADER_FIRMWARE, /* Firmware for the BootLoader */
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IMGU_FW_ACC_FIRMWARE /* Firmware for accelerations */
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};
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enum imgu_fw_acc_type {
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IMGU_FW_ACC_NONE, /* Normal binary */
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IMGU_FW_ACC_OUTPUT, /* Accelerator stage on output frame */
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IMGU_FW_ACC_VIEWFINDER, /* Accelerator stage on viewfinder frame */
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IMGU_FW_ACC_STANDALONE, /* Stand-alone acceleration */
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};
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struct imgu_fw_isp_parameter {
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u32 offset; /* Offset in isp_<mem> config, params, etc. */
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u32 size; /* Disabled if 0 */
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};
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struct imgu_fw_param_memory_offsets {
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struct {
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struct imgu_fw_isp_parameter lin; /* lin_vmem_params */
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struct imgu_fw_isp_parameter tnr3; /* tnr3_vmem_params */
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struct imgu_fw_isp_parameter xnr3; /* xnr3_vmem_params */
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} vmem;
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struct {
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struct imgu_fw_isp_parameter tnr;
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struct imgu_fw_isp_parameter tnr3; /* tnr3_params */
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struct imgu_fw_isp_parameter xnr3; /* xnr3_params */
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struct imgu_fw_isp_parameter plane_io_config; /* 192 bytes */
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struct imgu_fw_isp_parameter rgbir; /* rgbir_params */
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} dmem;
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};
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struct imgu_fw_config_memory_offsets {
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struct {
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struct imgu_fw_isp_parameter iterator;
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struct imgu_fw_isp_parameter dvs;
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struct imgu_fw_isp_parameter output;
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struct imgu_fw_isp_parameter raw;
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struct imgu_fw_isp_parameter input_yuv;
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struct imgu_fw_isp_parameter tnr;
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struct imgu_fw_isp_parameter tnr3;
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struct imgu_fw_isp_parameter ref;
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} dmem;
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};
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struct imgu_fw_state_memory_offsets {
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struct {
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struct imgu_fw_isp_parameter tnr;
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struct imgu_fw_isp_parameter tnr3;
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struct imgu_fw_isp_parameter ref;
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} dmem;
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};
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union imgu_fw_all_memory_offsets {
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struct {
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u64 imgu_fw_mem_offsets[3]; /* params, config, state */
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} offsets;
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struct {
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u64 ptr;
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} array[IMGU_ABI_PARAM_CLASS_NUM];
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};
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struct imgu_fw_binary_xinfo {
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/* Part that is of interest to the SP. */
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struct imgu_abi_binary_info sp;
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/* Rest of the binary info, only interesting to the host. */
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u32 type; /* enum imgu_fw_acc_type */
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u32 num_output_formats __aligned(8);
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u32 output_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */
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/* number of supported vf formats */
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u32 num_vf_formats __aligned(8);
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/* types of supported vf formats */
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u32 vf_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */
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u8 num_output_pins;
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imgu_fw_ptr xmem_addr;
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u64 imgu_fw_blob_descr_ptr __aligned(8);
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u32 blob_index __aligned(8);
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union imgu_fw_all_memory_offsets mem_offsets __aligned(8);
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struct imgu_fw_binary_xinfo *next __aligned(8);
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};
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struct imgu_fw_sp_info {
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u32 init_dmem_data; /* data sect config, stored to dmem */
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u32 per_frame_data; /* Per frame data, stored to dmem */
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u32 group; /* Per pipeline data, loaded by dma */
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u32 output; /* SP output data, loaded by dmem */
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u32 host_sp_queue; /* Host <-> SP queues */
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u32 host_sp_com; /* Host <-> SP commands */
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u32 isp_started; /* P'ed from sensor thread, csim only */
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u32 sw_state; /* Polled from css, enum imgu_abi_sp_swstate */
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u32 host_sp_queues_initialized; /* Polled from the SP */
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u32 sleep_mode; /* different mode to halt SP */
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u32 invalidate_tlb; /* inform SP to invalidate mmu TLB */
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u32 debug_buffer_ddr_address; /* the addr of DDR debug queue */
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/* input system perf count array */
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u32 perf_counter_input_system_error;
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u32 threads_stack; /* sp thread's stack pointers */
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u32 threads_stack_size; /* sp thread's stack sizes */
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u32 curr_binary_id; /* current binary id */
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u32 raw_copy_line_count; /* raw copy line counter */
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u32 ddr_parameter_address; /* acc param ddrptr, sp dmem */
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u32 ddr_parameter_size; /* acc param size, sp dmem */
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/* Entry functions */
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u32 sp_entry; /* The SP entry function */
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u32 tagger_frames_addr; /* Base address of tagger state */
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};
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struct imgu_fw_bl_info {
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u32 num_dma_cmds; /* Number of cmds sent by CSS */
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u32 dma_cmd_list; /* Dma command list sent by CSS */
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u32 sw_state; /* Polled from css, enum imgu_abi_bl_swstate */
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/* Entry functions */
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u32 bl_entry; /* The SP entry function */
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};
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struct imgu_fw_acc_info {
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u32 per_frame_data; /* Dummy for now */
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||||
};
|
||||
|
||||
union imgu_fw_union {
|
||||
struct imgu_fw_binary_xinfo isp; /* ISP info */
|
||||
struct imgu_fw_sp_info sp; /* SP info */
|
||||
struct imgu_fw_sp_info sp1; /* SP1 info */
|
||||
struct imgu_fw_bl_info bl; /* Bootloader info */
|
||||
struct imgu_fw_acc_info acc; /* Accelerator info */
|
||||
};
|
||||
|
||||
struct imgu_fw_info {
|
||||
size_t header_size; /* size of fw header */
|
||||
u32 type __aligned(8); /* enum imgu_fw_type */
|
||||
union imgu_fw_union info; /* Binary info */
|
||||
struct imgu_abi_blob_info blob; /* Blob info */
|
||||
/* Dynamic part */
|
||||
u64 next;
|
||||
|
||||
u32 loaded __aligned(8); /* Firmware has been loaded */
|
||||
const u64 isp_code __aligned(8); /* ISP pointer to code */
|
||||
/* Firmware handle between user space and kernel */
|
||||
u32 handle __aligned(8);
|
||||
/* Sections to copy from/to ISP */
|
||||
struct imgu_abi_isp_param_segments mem_initializers;
|
||||
/* Initializer for local ISP memories */
|
||||
};
|
||||
|
||||
struct imgu_fw_bi_file_h {
|
||||
char version[64]; /* branch tag + week day + time */
|
||||
int binary_nr; /* Number of binaries */
|
||||
unsigned int h_size; /* sizeof(struct imgu_fw_bi_file_h) */
|
||||
};
|
||||
|
||||
struct imgu_fw_header {
|
||||
struct imgu_fw_bi_file_h file_header;
|
||||
struct imgu_fw_info binary_header[1]; /* binary_nr items */
|
||||
};
|
||||
|
||||
/******************* Firmware functions *******************/
|
||||
|
||||
int ipu3_css_fw_init(struct ipu3_css *css);
|
||||
void ipu3_css_fw_cleanup(struct ipu3_css *css);
|
||||
|
||||
unsigned int ipu3_css_fw_obgrid_size(const struct imgu_fw_info *bi);
|
||||
void *ipu3_css_fw_pipeline_params(struct ipu3_css *css,
|
||||
enum imgu_abi_param_class c,
|
||||
enum imgu_abi_memories m,
|
||||
struct imgu_fw_isp_parameter *par,
|
||||
size_t par_size, void *binary_params);
|
||||
|
||||
#endif
|
Reference in New Issue
Block a user