xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse

Browse Source 
[ Upstream commit 4a8a77abf0e2b6468ba0281e33384cbec5fb476a ]

The fuse consists of 64 bits, with this statement we're supposed to get
the upper 32 bits but it actually read out of bounds and got 0 instead
of the desired value which lead to the "PVS bin not set." codepath being
run resetting our pvs value.

Fixes: a8811ec764 ("cpufreq: qcom: Add support for krait based socs")
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Luca Weiss
2022-01-30 12:45:35 +01:00
committed by Greg Kroah-Hartman
parent f90ad94322
commit 091704a9a7
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/cpufreq/qcom-cpufreq-nvmem.c
View File

@@ -130,7 +130,7 @@ static void get_krait_bin_format_b(struct device *cpu_dev,
} }
/* Check PVS_BLOW_STATUS */ /* Check PVS_BLOW_STATUS */
pte_efuse = *(((u32 *)buf) + 4); pte_efuse = *(((u32 *)buf) + 1);
pte_efuse &= BIT(21); pte_efuse &= BIT(21);
if (pte_efuse) { if (pte_efuse) {
dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);