arm64: bitops: patch in lse instructions when supported by the CPU
On CPUs which support the LSE atomic instructions introduced in ARMv8.1, it makes sense to use them in preference to ll/sc sequences. This patch introduces runtime patching of our bitops functions so that LSE atomic instructions are used instead. Reviewed-by: Steve Capper <steve.capper@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@@ -18,52 +18,57 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/lse.h>
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/*
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* x0: bits 5:0 bit offset
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* bits 31:6 word offset
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* x1: address
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*/
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.macro bitop, name, instr
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.macro bitop, name, llsc, lse
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ENTRY( \name )
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and w3, w0, #63 // Get bit offset
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eor w0, w0, w3 // Clear low bits
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mov x2, #1
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add x1, x1, x0, lsr #3 // Get word offset
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lsl x3, x2, x3 // Create mask
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1: ldxr x2, [x1]
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\instr x2, x2, x3
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stxr w0, x2, [x1]
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cbnz w0, 1b
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alt_lse "1: ldxr x2, [x1]", "\lse x3, [x1]"
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alt_lse " \llsc x2, x2, x3", "nop"
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alt_lse " stxr w0, x2, [x1]", "nop"
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alt_lse " cbnz w0, 1b", "nop"
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ret
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ENDPROC(\name )
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.endm
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.macro testop, name, instr
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.macro testop, name, llsc, lse
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ENTRY( \name )
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and w3, w0, #63 // Get bit offset
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eor w0, w0, w3 // Clear low bits
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mov x2, #1
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add x1, x1, x0, lsr #3 // Get word offset
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lsl x4, x2, x3 // Create mask
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1: ldxr x2, [x1]
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lsr x0, x2, x3 // Save old value of bit
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\instr x2, x2, x4 // toggle bit
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stlxr w5, x2, [x1]
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cbnz w5, 1b
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dmb ish
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alt_lse "1: ldxr x2, [x1]", "\lse x4, x2, [x1]"
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lsr x0, x2, x3
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alt_lse " \llsc x2, x2, x4", "nop"
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alt_lse " stlxr w5, x2, [x1]", "nop"
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alt_lse " cbnz w5, 1b", "nop"
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alt_lse " dmb ish", "nop"
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and x0, x0, #1
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3: ret
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ret
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ENDPROC(\name )
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.endm
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/*
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* Atomic bit operations.
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*/
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bitop change_bit, eor
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bitop clear_bit, bic
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bitop set_bit, orr
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bitop change_bit, eor, steor
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bitop clear_bit, bic, stclr
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bitop set_bit, orr, stset
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testop test_and_change_bit, eor
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testop test_and_clear_bit, bic
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testop test_and_set_bit, orr
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testop test_and_change_bit, eor, ldeoral
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testop test_and_clear_bit, bic, ldclral
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testop test_and_set_bit, orr, ldsetal
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