csky: Exception handling and mm-fault
This patch adds exception handling code, cpuinfo and mm-fault code. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Guo Ren
79
arch/csky/kernel/cpu-probe.c
Normal file
79
arch/csky/kernel/cpu-probe.c
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@@ -0,0 +1,79 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/of.h>
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#include <linux/init.h>
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#include <linux/seq_file.h>
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#include <linux/memblock.h>
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#include <abi/reg_ops.h>
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static void percpu_print(void *arg)
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{
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struct seq_file *m = (struct seq_file *)arg;
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unsigned int cur, next, i;
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seq_printf(m, "processor : %d\n", smp_processor_id());
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seq_printf(m, "C-SKY CPU model : %s\n", CSKYCPU_DEF_NAME);
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/* read processor id, max is 100 */
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cur = mfcr("cr13");
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for (i = 0; i < 100; i++) {
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seq_printf(m, "product info[%d] : 0x%08x\n", i, cur);
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next = mfcr("cr13");
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/* some CPU only has one id reg */
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if (cur == next)
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break;
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cur = next;
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/* cpid index is 31-28, reset */
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if (!(next >> 28)) {
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while ((mfcr("cr13") >> 28) != i);
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break;
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}
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}
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/* CPU feature regs, setup by bootloader or gdbinit */
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seq_printf(m, "hint (CPU funcs): 0x%08x\n", mfcr_hint());
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seq_printf(m, "ccr (L1C & MMU): 0x%08x\n", mfcr("cr18"));
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seq_printf(m, "ccr2 (L2C) : 0x%08x\n", mfcr_ccr2());
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seq_printf(m, "\n");
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}
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static int c_show(struct seq_file *m, void *v)
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{
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int cpu;
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for_each_online_cpu(cpu)
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smp_call_function_single(cpu, percpu_print, m, true);
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#ifdef CSKY_ARCH_VERSION
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seq_printf(m, "arch-version : %s\n", CSKY_ARCH_VERSION);
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seq_printf(m, "\n");
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#endif
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v) {}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show,
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};
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396
arch/csky/kernel/entry.S
Normal file
396
arch/csky/kernel/entry.S
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@@ -0,0 +1,396 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/linkage.h>
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#include <abi/entry.h>
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#include <abi/pgtable-bits.h>
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#include <asm/errno.h>
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#include <asm/setup.h>
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#include <asm/unistd.h>
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#include <asm/asm-offsets.h>
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#include <linux/threads.h>
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#define PTE_INDX_MSK 0xffc
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#define PTE_INDX_SHIFT 10
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#define _PGDIR_SHIFT 22
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.macro tlbop_begin name, val0, val1, val2
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ENTRY(csky_\name)
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mtcr a3, ss2
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mtcr r6, ss3
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mtcr a2, ss4
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RD_PGDR r6
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RD_MEH a3
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#ifdef CONFIG_CPU_HAS_TLBI
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tlbi.vaas a3
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sync.is
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btsti a3, 31
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bf 1f
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RD_PGDR_K r6
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1:
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#else
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bgeni a2, 31
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WR_MCIR a2
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bgeni a2, 25
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WR_MCIR a2
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#endif
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bclri r6, 0
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lrw a2, PHYS_OFFSET
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subu r6, a2
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bseti r6, 31
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mov a2, a3
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lsri a2, _PGDIR_SHIFT
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lsli a2, 2
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addu r6, a2
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ldw r6, (r6)
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lrw a2, PHYS_OFFSET
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subu r6, a2
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bseti r6, 31
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lsri a3, PTE_INDX_SHIFT
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lrw a2, PTE_INDX_MSK
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and a3, a2
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addu r6, a3
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ldw a3, (r6)
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movi a2, (_PAGE_PRESENT | \val0)
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and a3, a2
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cmpne a3, a2
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bt \name
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/* First read/write the page, just update the flags */
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ldw a3, (r6)
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bgeni a2, PAGE_VALID_BIT
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bseti a2, PAGE_ACCESSED_BIT
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bseti a2, \val1
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bseti a2, \val2
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or a3, a2
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stw a3, (r6)
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/* Some cpu tlb-hardrefill bypass the cache */
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#ifdef CONFIG_CPU_NEED_TLBSYNC
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movi a2, 0x22
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bseti a2, 6
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mtcr r6, cr22
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mtcr a2, cr17
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sync
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#endif
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mfcr a3, ss2
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mfcr r6, ss3
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mfcr a2, ss4
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rte
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\name:
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mfcr a3, ss2
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mfcr r6, ss3
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mfcr a2, ss4
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SAVE_ALL EPC_KEEP
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.endm
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.macro tlbop_end is_write
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RD_MEH a2
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psrset ee, ie
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mov a0, sp
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movi a1, \is_write
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jbsr do_page_fault
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movi r11_sig, 0 /* r11 = 0, Not a syscall. */
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jmpi ret_from_exception
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.endm
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.text
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tlbop_begin tlbinvalidl, _PAGE_READ, PAGE_VALID_BIT, PAGE_ACCESSED_BIT
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tlbop_end 0
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tlbop_begin tlbinvalids, _PAGE_WRITE, PAGE_DIRTY_BIT, PAGE_MODIFIED_BIT
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tlbop_end 1
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tlbop_begin tlbmodified, _PAGE_WRITE, PAGE_DIRTY_BIT, PAGE_MODIFIED_BIT
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#ifndef CONFIG_CPU_HAS_LDSTEX
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jbsr csky_cmpxchg_fixup
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#endif
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tlbop_end 1
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ENTRY(csky_systemcall)
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SAVE_ALL EPC_INCREASE
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psrset ee, ie
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/* Stack frame for syscall, origin call set_esp0 */
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mov r12, sp
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bmaski r11, 13
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andn r12, r11
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bgeni r11, 9
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addi r11, 32
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addu r12, r11
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st sp, (r12, 0)
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lrw r11, __NR_syscalls
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cmphs syscallid, r11 /* Check nr of syscall */
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bt ret_from_exception
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lrw r13, sys_call_table
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ixw r13, syscallid
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ldw r11, (r13)
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cmpnei r11, 0
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bf ret_from_exception
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mov r9, sp
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bmaski r10, THREAD_SHIFT
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andn r9, r10
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ldw r8, (r9, TINFO_FLAGS)
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btsti r8, TIF_SYSCALL_TRACE
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bt 1f
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#if defined(__CSKYABIV2__)
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subi sp, 8
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stw r5, (sp, 0x4)
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stw r4, (sp, 0x0)
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jsr r11 /* Do system call */
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addi sp, 8
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#else
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jsr r11
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#endif
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stw a0, (sp, LSAVE_A0) /* Save return value */
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jmpi ret_from_exception
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1:
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movi a0, 0 /* enter system call */
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mov a1, sp /* sp = pt_regs pointer */
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jbsr syscall_trace
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/* Prepare args before do system call */
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ldw a0, (sp, LSAVE_A0)
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ldw a1, (sp, LSAVE_A1)
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ldw a2, (sp, LSAVE_A2)
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ldw a3, (sp, LSAVE_A3)
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#if defined(__CSKYABIV2__)
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subi sp, 8
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stw r5, (sp, 0x4)
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stw r4, (sp, 0x0)
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#else
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ldw r6, (sp, LSAVE_A4)
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ldw r7, (sp, LSAVE_A5)
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#endif
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jsr r11 /* Do system call */
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#if defined(__CSKYABIV2__)
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addi sp, 8
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#endif
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stw a0, (sp, LSAVE_A0) /* Save return value */
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movi a0, 1 /* leave system call */
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mov a1, sp /* sp = pt_regs pointer */
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jbsr syscall_trace
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syscall_exit_work:
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ld syscallid, (sp, LSAVE_PSR)
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btsti syscallid, 31
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bt 2f
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jmpi resume_userspace
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2: RESTORE_ALL
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ENTRY(ret_from_kernel_thread)
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jbsr schedule_tail
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mov a0, r8
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jsr r9
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jbsr ret_from_exception
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ENTRY(ret_from_fork)
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jbsr schedule_tail
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mov r9, sp
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bmaski r10, THREAD_SHIFT
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andn r9, r10
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ldw r8, (r9, TINFO_FLAGS)
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movi r11_sig, 1
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btsti r8, TIF_SYSCALL_TRACE
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bf 3f
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movi a0, 1
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mov a1, sp /* sp = pt_regs pointer */
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jbsr syscall_trace
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3:
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jbsr ret_from_exception
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ret_from_exception:
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ld syscallid, (sp, LSAVE_PSR)
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btsti syscallid, 31
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bt 1f
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/*
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* Load address of current->thread_info, Then get address of task_struct
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* Get task_needreshed in task_struct
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*/
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mov r9, sp
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bmaski r10, THREAD_SHIFT
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andn r9, r10
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resume_userspace:
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ldw r8, (r9, TINFO_FLAGS)
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andi r8, (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED)
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cmpnei r8, 0
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bt exit_work
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1: RESTORE_ALL
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exit_work:
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mov a0, sp /* Stack address is arg[0] */
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jbsr set_esp0 /* Call C level */
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btsti r8, TIF_NEED_RESCHED
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bt work_resched
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/* If thread_info->flag is empty, RESTORE_ALL */
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cmpnei r8, 0
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bf 1b
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mov a1, sp
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mov a0, r8
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mov a2, r11_sig /* syscall? */
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btsti r8, TIF_SIGPENDING /* delivering a signal? */
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/* prevent further restarts(set r11 = 0) */
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clrt r11_sig
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jbsr do_notify_resume /* do signals */
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br resume_userspace
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work_resched:
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lrw syscallid, ret_from_exception
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mov r15, syscallid /* Return address in link */
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jmpi schedule
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ENTRY(sys_rt_sigreturn)
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movi r11_sig, 0
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jmpi do_rt_sigreturn
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ENTRY(csky_trap)
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SAVE_ALL EPC_KEEP
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psrset ee
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movi r11_sig, 0 /* r11 = 0, Not a syscall. */
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mov a0, sp /* Push Stack pointer arg */
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jbsr trap_c /* Call C-level trap handler */
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jmpi ret_from_exception
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/*
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* Prototype from libc for abiv1:
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* register unsigned int __result asm("a0");
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* asm( "trap 3" :"=r"(__result)::);
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*/
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ENTRY(csky_get_tls)
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USPTOKSP
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/* increase epc for continue */
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mfcr a0, epc
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INCTRAP a0
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mtcr a0, epc
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/* get current task thread_info with kernel 8K stack */
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bmaski a0, THREAD_SHIFT
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not a0
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subi sp, 1
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and a0, sp
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addi sp, 1
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/* get tls */
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ldw a0, (a0, TINFO_TP_VALUE)
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KSPTOUSP
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rte
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ENTRY(csky_irq)
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SAVE_ALL EPC_KEEP
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psrset ee
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movi r11_sig, 0 /* r11 = 0, Not a syscall. */
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#ifdef CONFIG_PREEMPT
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mov r9, sp /* Get current stack pointer */
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bmaski r10, THREAD_SHIFT
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andn r9, r10 /* Get thread_info */
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/*
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* Get task_struct->stack.preempt_count for current,
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* and increase 1.
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*/
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ldw r8, (r9, TINFO_PREEMPT)
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addi r8, 1
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stw r8, (r9, TINFO_PREEMPT)
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#endif
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mov a0, sp
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jbsr csky_do_IRQ
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#ifdef CONFIG_PREEMPT
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subi r8, 1
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stw r8, (r9, TINFO_PREEMPT)
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cmpnei r8, 0
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bt 2f
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ldw r8, (r9, TINFO_FLAGS)
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btsti r8, TIF_NEED_RESCHED
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bf 2f
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1:
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jbsr preempt_schedule_irq /* irq en/disable is done inside */
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ldw r7, (r9, TINFO_FLAGS) /* get new tasks TI_FLAGS */
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btsti r7, TIF_NEED_RESCHED
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bt 1b /* go again */
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#endif
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2:
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jmpi ret_from_exception
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/*
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* a0 = prev task_struct *
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* a1 = next task_struct *
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* a0 = return next
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*/
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ENTRY(__switch_to)
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lrw a3, TASK_THREAD
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addu a3, a0
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mfcr a2, psr /* Save PSR value */
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stw a2, (a3, THREAD_SR) /* Save PSR in task struct */
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bclri a2, 6 /* Disable interrupts */
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mtcr a2, psr
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SAVE_SWITCH_STACK
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stw sp, (a3, THREAD_KSP)
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#ifdef CONFIG_CPU_HAS_HILO
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lrw r10, THREAD_DSPHI
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add r10, a3
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mfhi r6
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mflo r7
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stw r6, (r10, 0) /* THREAD_DSPHI */
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stw r7, (r10, 4) /* THREAD_DSPLO */
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mfcr r6, cr14
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stw r6, (r10, 8) /* THREAD_DSPCSR */
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#endif
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/* Set up next process to run */
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lrw a3, TASK_THREAD
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addu a3, a1
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ldw sp, (a3, THREAD_KSP) /* Set next kernel sp */
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#ifdef CONFIG_CPU_HAS_HILO
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lrw r10, THREAD_DSPHI
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add r10, a3
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ldw r6, (r10, 8) /* THREAD_DSPCSR */
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mtcr r6, cr14
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ldw r6, (r10, 0) /* THREAD_DSPHI */
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ldw r7, (r10, 4) /* THREAD_DSPLO */
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mthi r6
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mtlo r7
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#endif
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ldw a2, (a3, THREAD_SR) /* Set next PSR */
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mtcr a2, psr
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#if defined(__CSKYABIV2__)
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addi r7, a1, TASK_THREAD_INFO
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ldw tls, (r7, TINFO_TP_VALUE)
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#endif
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RESTORE_SWITCH_STACK
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rts
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ENDPROC(__switch_to)
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169
arch/csky/kernel/traps.c
Normal file
169
arch/csky/kernel/traps.c
Normal file
@@ -0,0 +1,169 @@
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// SPDX-License-Identifier: GPL-2.0
|
||||
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
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#include <linux/module.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/kallsyms.h>
|
||||
#include <linux/rtc.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/siginfo.h>
|
||||
|
||||
#include <asm/mmu_context.h>
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_FPU
|
||||
#include <abi/fpu.h>
|
||||
#endif
|
||||
|
||||
/* Defined in entry.S */
|
||||
asmlinkage void csky_trap(void);
|
||||
|
||||
asmlinkage void csky_systemcall(void);
|
||||
asmlinkage void csky_cmpxchg(void);
|
||||
asmlinkage void csky_get_tls(void);
|
||||
asmlinkage void csky_irq(void);
|
||||
|
||||
asmlinkage void csky_tlbinvalidl(void);
|
||||
asmlinkage void csky_tlbinvalids(void);
|
||||
asmlinkage void csky_tlbmodified(void);
|
||||
|
||||
/* Defined in head.S */
|
||||
asmlinkage void _start_smp_secondary(void);
|
||||
|
||||
void __init pre_trap_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
mtcr("vbr", vec_base);
|
||||
|
||||
for (i = 1; i < 128; i++)
|
||||
VEC_INIT(i, csky_trap);
|
||||
}
|
||||
|
||||
void __init trap_init(void)
|
||||
{
|
||||
VEC_INIT(VEC_AUTOVEC, csky_irq);
|
||||
|
||||
/* setup trap0 trap2 trap3 */
|
||||
VEC_INIT(VEC_TRAP0, csky_systemcall);
|
||||
VEC_INIT(VEC_TRAP2, csky_cmpxchg);
|
||||
VEC_INIT(VEC_TRAP3, csky_get_tls);
|
||||
|
||||
/* setup MMU TLB exception */
|
||||
VEC_INIT(VEC_TLBINVALIDL, csky_tlbinvalidl);
|
||||
VEC_INIT(VEC_TLBINVALIDS, csky_tlbinvalids);
|
||||
VEC_INIT(VEC_TLBMODIFIED, csky_tlbmodified);
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_FPU
|
||||
init_fpu();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
mtcr("cr<28, 0>", virt_to_phys(vec_base));
|
||||
|
||||
VEC_INIT(VEC_RESET, (void *)virt_to_phys(_start_smp_secondary));
|
||||
#endif
|
||||
}
|
||||
|
||||
void die_if_kernel(char *str, struct pt_regs *regs, int nr)
|
||||
{
|
||||
if (user_mode(regs))
|
||||
return;
|
||||
|
||||
console_verbose();
|
||||
pr_err("%s: %08x\n", str, nr);
|
||||
show_regs(regs);
|
||||
add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
|
||||
do_exit(SIGSEGV);
|
||||
}
|
||||
|
||||
void buserr(struct pt_regs *regs)
|
||||
{
|
||||
#ifdef CONFIG_CPU_CK810
|
||||
static unsigned long prev_pc;
|
||||
|
||||
if ((regs->pc == prev_pc) && prev_pc != 0) {
|
||||
prev_pc = 0;
|
||||
} else {
|
||||
prev_pc = regs->pc;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
die_if_kernel("Kernel mode BUS error", regs, 0);
|
||||
|
||||
pr_err("User mode Bus Error\n");
|
||||
show_regs(regs);
|
||||
|
||||
current->thread.esp0 = (unsigned long) regs;
|
||||
force_sig_fault(SIGSEGV, 0, (void __user *)regs->pc, current);
|
||||
}
|
||||
|
||||
#define USR_BKPT 0x1464
|
||||
asmlinkage void trap_c(struct pt_regs *regs)
|
||||
{
|
||||
int sig;
|
||||
unsigned long vector;
|
||||
siginfo_t info;
|
||||
|
||||
vector = (mfcr("psr") >> 16) & 0xff;
|
||||
|
||||
switch (vector) {
|
||||
case VEC_ZERODIV:
|
||||
sig = SIGFPE;
|
||||
break;
|
||||
/* ptrace */
|
||||
case VEC_TRACE:
|
||||
info.si_code = TRAP_TRACE;
|
||||
sig = SIGTRAP;
|
||||
break;
|
||||
case VEC_ILLEGAL:
|
||||
#ifndef CONFIG_CPU_NO_USER_BKPT
|
||||
if (*(uint16_t *)instruction_pointer(regs) != USR_BKPT)
|
||||
#endif
|
||||
{
|
||||
sig = SIGILL;
|
||||
break;
|
||||
}
|
||||
/* gdbserver breakpoint */
|
||||
case VEC_TRAP1:
|
||||
/* jtagserver breakpoint */
|
||||
case VEC_BREAKPOINT:
|
||||
info.si_code = TRAP_BRKPT;
|
||||
sig = SIGTRAP;
|
||||
break;
|
||||
case VEC_ACCESS:
|
||||
return buserr(regs);
|
||||
#ifdef CONFIG_CPU_NEED_SOFTALIGN
|
||||
case VEC_ALIGN:
|
||||
return csky_alignment(regs);
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_HAS_FPU
|
||||
case VEC_FPE:
|
||||
return fpu_fpe(regs);
|
||||
case VEC_PRIV:
|
||||
if (fpu_libc_helper(regs))
|
||||
return;
|
||||
#endif
|
||||
default:
|
||||
sig = SIGSEGV;
|
||||
break;
|
||||
}
|
||||
send_sig(sig, current, 0);
|
||||
}
|
||||
|
||||
asmlinkage void set_esp0(unsigned long ssp)
|
||||
{
|
||||
current->thread.esp0 = ssp;
|
||||
}
|
||||
Reference in New Issue
Block a user