Merge tag 'mmc-v4.8' of git://git.linaro.org/people/ulf.hansson/mmc
Pull MMC updates from Ulf Hansson: "MMC core: - A couple of changes to improve the support for erase/discard/trim cmds - Add eMMC HS400 enhanced strobe support - Show OCR and DSR registers in SYSFS for MMC/SD cards - Correct and improve busy detection logic for MMC switch (CMD6) cmds - Disable HPI cmds for certain broken Hynix eMMC cards - Allow MMC hosts to specify non-support for SD and MMC cmds - Some minor additional fixes MMC host: - sdhci: Re-works, fixes and clean-ups - sdhci: Add HW auto re-tuning support - sdhci: Re-factor code to prepare for adding support for eMMC CMDQ - sdhci-esdhc-imx: Fixes and clean-ups - sdhci-esdhc-imx: Update system PM support - sdhci-esdhc-imx: Enable HW auto re-tuning - sdhci-bcm2835: Remove driver as sdhci-iproc is used instead - sdhci-brcmstb: Add new driver for Broadcom BRCMSTB SoCs - sdhci-msm: Add support for UHS cards - sdhci-tegra: Improve support for UHS cards - sdhci-of-arasan: Update phy support for Rockchip SoCs - sdhci-of-arasan: Deploy enhanced strobe support - dw_mmc: Some fixes and clean-ups - dw_mmc: Enable support for erase/discard/trim cmds - dw_mmc: Enable CMD23 support - mediatek: Some fixes related to the eMMC HS400 support - sh_mmcif: Improve support for HW busy detection - rtsx_pci: Enable support for erase/discard/trim cmds" * tag 'mmc-v4.8' of git://git.linaro.org/people/ulf.hansson/mmc: (135 commits) mmc: rtsx_pci: Remove deprecated create_singlethread_workqueue mmc: rtsx_pci: Enable MMC_CAP_ERASE to allow erase/discard/trim requests mmc: rtsx_pci: Use the provided busy timeout from the mmc core mmc: sdhci-pltfm: Drop define for SDHCI_PLTFM_PMOPS mmc: sdhci-pltfm: Convert to use the SET_SYSTEM_SLEEP_PM_OPS mmc: sdhci-pltfm: Make sdhci_pltfm_suspend|resume() static mmc: sdhci-esdhc-imx: Use common sdhci_suspend|resume_host() mmc: sdhci-esdhc-imx: Assign system PM ops within #ifdef CONFIG_PM_SLEEP mmc: sdhci-sirf: Remove non needed #ifdef CONFIG_PM* for dev_pm_ops mmc: sdhci-s3c: Remove non needed #ifdef CONFIG_PM for dev_pm_ops mmc: sdhci-pxav3: Remove non needed #ifdef CONFIG_PM for dev_pm_ops mmc: sdhci-of-esdhc: Simplify code by using SIMPLE_DEV_PM_OPS mmc: sdhci-acpi: Simplify code by using SET_SYSTEM_SLEEP_PM_OPS mmc: sdhci-pci-core: Simplify code by using SET_SYSTEM_SLEEP_PM_OPS mmc: Change the max discard sectors and erase response when HW busy detect phy: rockchip-emmc: Wait even longer for the DLL to lock phy: rockchip-emmc: Be tolerant to card clock of 0 in power on mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes mmc: sdhci-msm: Add support for UHS cards mmc: sdhci-msm: Add set_uhs_signaling() implementation ...
このコミットが含まれているのは:
Linus Torvalds
@@ -14,6 +14,7 @@
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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@@ -31,42 +32,64 @@
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((val) << (shift) | (mask) << ((shift) + 16))
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/* Register definition */
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#define GRF_EMMCPHY_CON0 0x0
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#define GRF_EMMCPHY_CON1 0x4
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#define GRF_EMMCPHY_CON2 0x8
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#define GRF_EMMCPHY_CON3 0xc
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#define GRF_EMMCPHY_CON4 0x10
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#define GRF_EMMCPHY_CON5 0x14
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#define GRF_EMMCPHY_CON6 0x18
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#define GRF_EMMCPHY_STATUS 0x20
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#define GRF_EMMCPHY_CON0 0x0
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#define GRF_EMMCPHY_CON1 0x4
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#define GRF_EMMCPHY_CON2 0x8
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#define GRF_EMMCPHY_CON3 0xc
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#define GRF_EMMCPHY_CON4 0x10
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#define GRF_EMMCPHY_CON5 0x14
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#define GRF_EMMCPHY_CON6 0x18
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#define GRF_EMMCPHY_STATUS 0x20
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#define PHYCTRL_PDB_MASK 0x1
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#define PHYCTRL_PDB_SHIFT 0x0
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#define PHYCTRL_PDB_PWR_ON 0x1
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#define PHYCTRL_PDB_PWR_OFF 0x0
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#define PHYCTRL_ENDLL_MASK 0x1
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#define PHYCTRL_ENDLL_SHIFT 0x1
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#define PHYCTRL_ENDLL_ENABLE 0x1
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#define PHYCTRL_ENDLL_DISABLE 0x0
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#define PHYCTRL_CALDONE_MASK 0x1
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#define PHYCTRL_CALDONE_SHIFT 0x6
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#define PHYCTRL_CALDONE_DONE 0x1
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#define PHYCTRL_CALDONE_GOING 0x0
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#define PHYCTRL_DLLRDY_MASK 0x1
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#define PHYCTRL_DLLRDY_SHIFT 0x5
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#define PHYCTRL_DLLRDY_DONE 0x1
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#define PHYCTRL_DLLRDY_GOING 0x0
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#define PHYCTRL_PDB_MASK 0x1
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#define PHYCTRL_PDB_SHIFT 0x0
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#define PHYCTRL_PDB_PWR_ON 0x1
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#define PHYCTRL_PDB_PWR_OFF 0x0
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#define PHYCTRL_ENDLL_MASK 0x1
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#define PHYCTRL_ENDLL_SHIFT 0x1
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#define PHYCTRL_ENDLL_ENABLE 0x1
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#define PHYCTRL_ENDLL_DISABLE 0x0
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#define PHYCTRL_CALDONE_MASK 0x1
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#define PHYCTRL_CALDONE_SHIFT 0x6
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#define PHYCTRL_CALDONE_DONE 0x1
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#define PHYCTRL_CALDONE_GOING 0x0
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#define PHYCTRL_DLLRDY_MASK 0x1
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#define PHYCTRL_DLLRDY_SHIFT 0x5
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#define PHYCTRL_DLLRDY_DONE 0x1
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#define PHYCTRL_DLLRDY_GOING 0x0
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#define PHYCTRL_FREQSEL_200M 0x0
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#define PHYCTRL_FREQSEL_50M 0x1
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#define PHYCTRL_FREQSEL_100M 0x2
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#define PHYCTRL_FREQSEL_150M 0x3
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#define PHYCTRL_FREQSEL_MASK 0x3
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#define PHYCTRL_FREQSEL_SHIFT 0xc
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#define PHYCTRL_DR_MASK 0x7
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#define PHYCTRL_DR_SHIFT 0x4
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#define PHYCTRL_DR_50OHM 0x0
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#define PHYCTRL_DR_33OHM 0x1
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#define PHYCTRL_DR_66OHM 0x2
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#define PHYCTRL_DR_100OHM 0x3
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#define PHYCTRL_DR_40OHM 0x4
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#define PHYCTRL_OTAPDLYENA 0x1
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#define PHYCTRL_OTAPDLYENA_MASK 0x1
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#define PHYCTRL_OTAPDLYENA_SHIFT 0xb
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#define PHYCTRL_OTAPDLYSEL_MASK 0xf
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#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
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struct rockchip_emmc_phy {
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unsigned int reg_offset;
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struct regmap *reg_base;
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struct clk *emmcclk;
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};
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static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
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bool on_off)
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static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
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{
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
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unsigned int caldone;
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unsigned int dllrdy;
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unsigned int freqsel = PHYCTRL_FREQSEL_200M;
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unsigned long rate;
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unsigned long timeout;
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/*
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* Keep phyctrl_pdb and phyctrl_endll low to allow
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@@ -87,6 +110,43 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
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if (on_off == PHYCTRL_PDB_PWR_OFF)
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return 0;
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rate = clk_get_rate(rk_phy->emmcclk);
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if (rate != 0) {
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unsigned long ideal_rate;
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unsigned long diff;
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switch (rate) {
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case 1 ... 74999999:
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ideal_rate = 50000000;
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freqsel = PHYCTRL_FREQSEL_50M;
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break;
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case 75000000 ... 124999999:
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ideal_rate = 100000000;
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freqsel = PHYCTRL_FREQSEL_100M;
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break;
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case 125000000 ... 174999999:
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ideal_rate = 150000000;
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freqsel = PHYCTRL_FREQSEL_150M;
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break;
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default:
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ideal_rate = 200000000;
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break;
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};
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diff = (rate > ideal_rate) ?
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rate - ideal_rate : ideal_rate - rate;
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/*
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* In order for tuning delays to be accurate we need to be
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* pretty spot on for the DLL range, so warn if we're too
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* far off. Also warn if we're above the 200 MHz max. Don't
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* warn for really slow rates since we won't be tuning then.
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*/
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if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
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dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
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}
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/*
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* According to the user manual, calpad calibration
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* cycle takes more than 2us without the minimal recommended
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@@ -113,20 +173,62 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
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return -ETIMEDOUT;
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}
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/* Set the frequency of the DLL operation */
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON0,
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HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
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PHYCTRL_FREQSEL_SHIFT));
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/* Turn on the DLL */
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON6,
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HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
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PHYCTRL_ENDLL_MASK,
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PHYCTRL_ENDLL_SHIFT));
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/*
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* After enable analog DLL circuits, we need extra 10.2us
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* for dll to be ready for work.
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* We turned on the DLL even though the rate was 0 because we the
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* clock might be turned on later. ...but we can't wait for the DLL
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* to lock when the rate is 0 because it will never lock with no
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* input clock.
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*
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* Technically we should be checking the lock later when the clock
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* is turned on, but for now we won't.
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*/
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udelay(11);
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regmap_read(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
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&dllrdy);
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dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
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if (rate == 0)
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return 0;
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/*
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* After enabling analog DLL circuits docs say that we need 10.2 us if
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* our source clock is at 50 MHz and that lock time scales linearly
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* with clock speed. If we are powering on the PHY and the card clock
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* is super slow (like 100 kHZ) this could take as long as 5.1 ms as
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* per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
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* Hopefully we won't be running at 100 kHz, but we should still make
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* sure we wait long enough.
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*
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* NOTE: There appear to be corner cases where the DLL seems to take
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* extra long to lock for reasons that aren't understood. In some
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* extreme cases we've seen it take up to over 10ms (!). We'll be
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* generous and give it 50ms. We still busy wait here because:
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* - In most cases it should be super fast.
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* - This is not called lots during normal operation so it shouldn't
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* be a power or performance problem to busy wait. We expect it
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* only at boot / resume. In both cases, eMMC is probably on the
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* critical path so busy waiting a little extra time should be OK.
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*/
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timeout = jiffies + msecs_to_jiffies(50);
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do {
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udelay(1);
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regmap_read(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
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&dllrdy);
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dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
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if (dllrdy == PHYCTRL_DLLRDY_DONE)
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break;
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} while (!time_after(jiffies, timeout));
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if (dllrdy != PHYCTRL_DLLRDY_DONE) {
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pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
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return -ETIMEDOUT;
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@@ -135,33 +237,82 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
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return 0;
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}
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static int rockchip_emmc_phy_power_off(struct phy *phy)
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static int rockchip_emmc_phy_init(struct phy *phy)
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{
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
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int ret = 0;
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/* Power down emmc phy analog blocks */
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ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
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if (ret)
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return ret;
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/*
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* We purposely get the clock here and not in probe to avoid the
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* circular dependency problem. We expect:
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* - PHY driver to probe
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* - SDHCI driver to start probe
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* - SDHCI driver to register it's clock
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* - SDHCI driver to get the PHY
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* - SDHCI driver to init the PHY
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*
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* The clock is optional, so upon any error we just set to NULL.
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*
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* NOTE: we don't do anything special for EPROBE_DEFER here. Given the
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* above expected use case, EPROBE_DEFER isn't sensible to expect, so
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* it's just like any other error.
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*/
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rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
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if (IS_ERR(rk_phy->emmcclk)) {
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dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
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rk_phy->emmcclk = NULL;
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}
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return ret;
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}
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static int rockchip_emmc_phy_exit(struct phy *phy)
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{
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
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clk_put(rk_phy->emmcclk);
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return 0;
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}
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static int rockchip_emmc_phy_power_off(struct phy *phy)
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{
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/* Power down emmc phy analog blocks */
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return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
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}
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static int rockchip_emmc_phy_power_on(struct phy *phy)
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{
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
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int ret = 0;
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/* Drive impedance: 50 Ohm */
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON6,
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HIWORD_UPDATE(PHYCTRL_DR_50OHM,
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PHYCTRL_DR_MASK,
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PHYCTRL_DR_SHIFT));
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/* Output tap delay: enable */
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON0,
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HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
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PHYCTRL_OTAPDLYENA_MASK,
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PHYCTRL_OTAPDLYENA_SHIFT));
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/* Output tap delay */
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON0,
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HIWORD_UPDATE(4,
|
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PHYCTRL_OTAPDLYSEL_MASK,
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PHYCTRL_OTAPDLYSEL_SHIFT));
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/* Power up emmc phy analog blocks */
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ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
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if (ret)
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return ret;
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return 0;
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return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
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}
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static const struct phy_ops ops = {
|
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.init = rockchip_emmc_phy_init,
|
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.exit = rockchip_emmc_phy_exit,
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.power_on = rockchip_emmc_phy_power_on,
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.power_off = rockchip_emmc_phy_power_off,
|
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.owner = THIS_MODULE,
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