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hwrng: n2 - support new hardware register layout

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Add the new register layout constants and the requisite logic
for using them.

Signed-off-by: Shannon Nelson <shannon.nelson@oracle.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Esse commit está contido em:
Shannon Nelson
2017-01-12 10:52:48 -08:00
commit de Herbert Xu
pai becbc4940a
commit 07e25d43be
2 arquivos alterados com 132 adições e 44 exclusões
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36
drivers/char/hw_random/n2rng.h
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@@ -6,18 +6,34 @@
#ifndef _N2RNG_H
#define _N2RNG_H
#define RNG_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
#define RNG_CTL_WAIT_SHIFT 9
#define RNG_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
#define RNG_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
#define RNG_CTL_VCO_SHIFT 6
#define RNG_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
#define RNG_CTL_ASEL_SHIFT 4
/* ver1 devices - n2-rng, vf-rng, kt-rng */
#define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
#define RNG_v1_CTL_WAIT_SHIFT 9
#define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
#define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
#define RNG_v1_CTL_VCO_SHIFT 6
#define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
#define RNG_v1_CTL_ASEL_SHIFT 4
#define RNG_v1_CTL_ASEL_NOOUT 2
/* these are the same in v2 as in v1 */
#define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */
#define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */
#define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */
#define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */
/* ver2 devices - m4-rng, m7-rng */
#define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */
#define RNG_v2_CTL_WAIT_SHIFT 12
#define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */
#define RNG_v2_CTL_VCO 0x0000000000000300ULL /* VCO rate control */
#define RNG_v2_CTL_VCO_SHIFT 9
#define RNG_v2_CTL_PERF 0x0000000000000180ULL /* Perf */
#define RNG_v2_CTL_ASEL 0x0000000000000070ULL /* Analog MUX select */
#define RNG_v2_CTL_ASEL_SHIFT 4
#define RNG_v2_CTL_ASEL_NOOUT 7
#define HV_FAST_RNG_GET_DIAG_CTL 0x130
#define HV_FAST_RNG_CTL_READ 0x131
#define HV_FAST_RNG_CTL_WRITE 0x132
@@ -112,8 +128,10 @@ struct n2rng {
u64 scratch_control[HV_RNG_NUM_CONTROL];
#define SELFTEST_TICKS 38859
#define SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
#define RNG_v1_SELFTEST_TICKS 38859
#define RNG_v1_SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
#define RNG_v2_SELFTEST_TICKS 64
#define RNG_v2_SELFTEST_VAL ((u64)0xffffffffffffffff)
#define SELFTEST_POLY ((u64)0x231DCEE91262B8A3)
#define SELFTEST_MATCH_GOAL 6
#define SELFTEST_LOOPS_MAX 40000