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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

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Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for 4.7.  Here's the summary of
  the changes:

   - ATH79: Support for DTB passuing using the UHI boot protocol
   - ATH79: Remove support for builtin DTB.
   - ATH79: Add zboot debug serial support.
   - ATH79: Add initial support for Dragino MS14 (Dragine 2), Onion Omega
            and DPT-Module.
   - ATH79: Update devicetree clock support for AR9132 and AR9331.
   - ATH79: Cleanup the DT code.
   - ATH79: Support newer SOCs in ath79_ddr_ctrl_init.
   - ATH79: Fix regression in PCI window initialization.
   - BCM47xx: Move SPROM driver to drivers/firmware/
   - BCM63xx: Enable partition parser in defconfig.
   - BMIPS: BMIPS5000 has I cache filing from D cache
   - BMIPS: BMIPS: Add cpu-feature-overrides.h
   - BMIPS: Add Whirlwind support
   - BMIPS: Adjust mips-hpt-frequency for BCM7435
   - BMIPS: Remove maxcpus from BCM97435SVMB DTS
   - BMIPS: Add missing 7038 L1 register cells to BCM7435
   - BMIPS: Various tweaks to initialization code.
   - BMIPS: Enable partition parser in defconfig.
   - BMIPS: Cache tweaks.
   - BMIPS: Add UART, I2C and SATA devices to DT.
   - BMIPS: Add BCM6358 and BCM63268support
   - BMIPS: Add device tree example for BCM6358.
   - BMIPS: Improve Improve BCM6328 and BCM6368 device trees
   - Lantiq: Add support for device tree file from boot loader
   - Lantiq: Allow build with no built-in DT.
   - Loongson 3: Reserve 32MB for RS780E integrated GPU.
   - Loongson 3: Fix build error after ld-version.sh modification
   - Loongson 3: Move chipset ACPI code from drivers to arch.
   - Loongson 3: Speedup irq processing.
   - Loongson 3: Add basic Loongson 3A support.
   - Loongson 3: Set cache flush handlers to nop.
   - Loongson 3: Invalidate special TLBs when needed.
   - Loongson 3: Fast TLB refill handler.
   - MT7620: Fallback strategy for invalid syscfg0.
   - Netlogic: Fix CP0_EBASE redefinition warnings
   - Octeon: Initialization fixes
   - Octeon: Add DTS files for the D-Link DSR-1000N and EdgeRouter Lite
   - Octeon: Enable add Octeon-drivers in cavium_octeon_defconfig
   - Octeon: Correctly handle endian-swapped initramfs images.
   - Octeon: Support CN73xx, CN75xx and CN78xx.
   - Octeon: Remove dead code from cvmx-sysinfo.
   - Octeon: Extend number of supported CPUs past 32.
   - Octeon: Remove some code limiting NR_IRQS to 255.
   - Octeon: Simplify octeon_irq_ciu_gpio_set_type.
   - Octeon: Mark some functions __init in smp.c
   - Octeon: Octeon: Add Octeon III CN7xxx interface detection
   - PIC32: Add serial driver and bindings for it.
   - PIC32: Add PIC32 deadman timer driver and bindings.
   - PIC32: Add PIC32 clock timer driver and bindings.
   - Pistachio: Determine SoC revision during boot
   - Sibyte: Fix Kconfig dependencies of SIBYTE_BUS_WATCHER.
   - Sibyte: Strip redundant comments from bcm1480_regs.h.
   - Panic immediately if panic_on_oops is set.
   - module: fix incorrect IS_ERR_VALUE macro usage.
   - module: Make consistent use of pr_*
   - Remove no longer needed work_on_cpu() call.
   - Remove CONFIG_IPV6_PRIVACY from defconfigs.
   - Fix registers of non-crashing CPUs in dumps.
   - Handle MIPSisms in new vmcore_elf32_check_arch.
   - Select CONFIG_HANDLE_DOMAIN_IRQ and make it work.
   - Allow RIXI to be used on non-R2 or R6 cores.
   - Reserve nosave data for hibernation
   - Fix siginfo.h to use strict POSIX types.
   - Don't unwind user mode with EVA.
   - Fix watchpoint restoration
   - Ptrace watchpoints for R6.
   - Sync icache when it fills from dcache
   - I6400 I-cache fills from dcache.
   - Various MSA fixes.
   - Cleanup MIPS_CPU_* definitions.
   - Signal: Move generic copy_siginfo to signal.h
   - Signal: Fix uapi include in exported asm/siginfo.h
   - Timer fixes for sake of KVM.
   - XPA TLB refill fixes.
   - Treat perf counter feature
   - Update John Crispin's email address
   - Add PIC32 watchdog and bindings.
   - Handle R10000 LL/SC bug in set_pte()
   - cpufreq: Various fixes for Longson1.
   - R6: Fix R2 emulation.
   - mathemu: Cosmetic fix to ADDIUPC emulation, plenty of other small fixes
   - ELF: ABI and FP fixes.
   - Allow for relocatable kernel and use that to support KASLR.
   - Fix CPC_BASE_ADDR mask
   - Plenty fo smp-cps, CM, R6 and M6250 fixes.
   - Make reset_control_ops const.
   - Fix kernel command line handling of leading whitespace.
   - Cleanups to cache handling.
   - Add brcm, bcm6345-l1-intc device tree bindings.
   - Use generic clkdev.h header
   - Remove CLK_IS_ROOT usage.
   - Misc small cleanups.
   - CM: Fix compilation error when !MIPS_CM
   - oprofile: Fix a preemption issue
   - Detect DSP ASE v3 support:1"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (275 commits)
  MIPS: pic32mzda: fix getting timer clock rate.
  MIPS: ath79: fix regression in PCI window initialization
  MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs
  MIPS: Fix VZ probe gas errors with binutils <2.24
  MIPS: perf: Fix I6400 event numbers
  MIPS: DEC: Export `ioasic_ssr_lock' to modules
  MIPS: MSA: Fix a link error on `_init_msa_upper' with older GCC
  MIPS: CM: Fix compilation error when !MIPS_CM
  MIPS: Fix genvdso error on rebuild
  USB: ohci-jz4740: Remove obsolete driver
  MIPS: JZ4740: Probe OHCI platform device via DT
  MIPS: JZ4740: Qi LB60: Remove support for AVT2 variant
  MIPS: pistachio: Determine SoC revision during boot
  MIPS: BMIPS: Adjust mips-hpt-frequency for BCM7435
  mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type
  MIPS: Prevent "restoration" of MSA context in non-MSA kernels
  MIPS: cevt-r4k: Dynamically calculate min_delta_ns
  MIPS: malta-time: Take seconds into account
  MIPS: malta-time: Start GIC count before syncing to RTC
  MIPS: Force CPUs to lose FP context during mode switches
  ...
This commit is contained in:
Linus Torvalds
2016-05-19 10:02:26 -07:00
parent 0efacbbaee 6e4ad1b413
commit 07b75260eb
358 changed files with 14041 additions and 3435 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/platform/mips/Kconfig
View File

@@ -15,10 +15,6 @@ menuconfig MIPS_PLATFORM_DEVICES
if MIPS_PLATFORM_DEVICES
config MIPS_ACPI
bool
default y if LOONGSON_MACH3X
config CPU_HWMON
tristate "Loongson CPU HWMon Driver"
depends on LOONGSON_MACH3X

1
drivers/platform/mips/Makefile
View File

@@ -1,2 +1 @@
obj-$(CONFIG_MIPS_ACPI) += acpi_init.o
obj-$(CONFIG_CPU_HWMON) += cpu_hwmon.o

150
drivers/platform/mips/acpi_init.c
View File

@@ -1,150 +0,0 @@
#include <linux/io.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/export.h>
#define SBX00_ACPI_IO_BASE 0x800
#define SBX00_ACPI_IO_SIZE 0x100
#define ACPI_PM_EVT_BLK (SBX00_ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM_CNT_BLK (SBX00_ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PMA_CNT_BLK (SBX00_ACPI_IO_BASE + 0x0F) /* 1 byte */
#define ACPI_PM_TMR_BLK (SBX00_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define ACPI_GPE0_BLK (SBX00_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_END (SBX00_ACPI_IO_BASE + 0x80)
#define PM_INDEX 0xCD6
#define PM_DATA 0xCD7
#define PM2_INDEX 0xCD0
#define PM2_DATA 0xCD1
/*
* SCI interrupt need acpi space, allocate here
*/
static int __init register_acpi_resource(void)
{
request_region(SBX00_ACPI_IO_BASE, SBX00_ACPI_IO_SIZE, "acpi");
return 0;
}
static void pmio_write_index(u16 index, u8 reg, u8 value)
{
outb(reg, index);
outb(value, index + 1);
}
static u8 pmio_read_index(u16 index, u8 reg)
{
outb(reg, index);
return inb(index + 1);
}
void pm_iowrite(u8 reg, u8 value)
{
pmio_write_index(PM_INDEX, reg, value);
}
EXPORT_SYMBOL(pm_iowrite);
u8 pm_ioread(u8 reg)
{
return pmio_read_index(PM_INDEX, reg);
}
EXPORT_SYMBOL(pm_ioread);
void pm2_iowrite(u8 reg, u8 value)
{
pmio_write_index(PM2_INDEX, reg, value);
}
EXPORT_SYMBOL(pm2_iowrite);
u8 pm2_ioread(u8 reg)
{
return pmio_read_index(PM2_INDEX, reg);
}
EXPORT_SYMBOL(pm2_ioread);
static void acpi_hw_clear_status(void)
{
u16 value;
/* PMStatus: Clear WakeStatus/PwrBtnStatus */
value = inw(ACPI_PM_EVT_BLK);
value |= (1 << 8 | 1 << 15);
outw(value, ACPI_PM_EVT_BLK);
/* GPEStatus: Clear all generated events */
outl(inl(ACPI_GPE0_BLK), ACPI_GPE0_BLK);
}
void acpi_registers_setup(void)
{
u32 value;
/* PM Status Base */
pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xff);
pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
/* PM Control Base */
pm_iowrite(0x22, ACPI_PM_CNT_BLK & 0xff);
pm_iowrite(0x23, ACPI_PM_CNT_BLK >> 8);
/* GPM Base */
pm_iowrite(0x28, ACPI_GPE0_BLK & 0xff);
pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
/* ACPI End */
pm_iowrite(0x2e, ACPI_END & 0xff);
pm_iowrite(0x2f, ACPI_END >> 8);
/* IO Decode: When AcpiDecodeEnable set, South-Bridge uses the contents
* of the PM registers at index 0x20~0x2B to decode ACPI I/O address. */
pm_iowrite(0x0e, 1 << 3);
/* SCI_EN set */
outw(1, ACPI_PM_CNT_BLK);
/* Enable to generate SCI */
pm_iowrite(0x10, pm_ioread(0x10) | 1);
/* GPM3/GPM9 enable */
value = inl(ACPI_GPE0_BLK + 4);
outl(value | (1 << 14) | (1 << 22), ACPI_GPE0_BLK + 4);
/* Set GPM9 as input */
pm_iowrite(0x8d, pm_ioread(0x8d) & (~(1 << 1)));
/* Set GPM9 as non-output */
pm_iowrite(0x94, pm_ioread(0x94) | (1 << 3));
/* GPM3 config ACPI trigger SCIOUT */
pm_iowrite(0x33, pm_ioread(0x33) & (~(3 << 4)));
/* GPM9 config ACPI trigger SCIOUT */
pm_iowrite(0x3d, pm_ioread(0x3d) & (~(3 << 2)));
/* GPM3 config falling edge trigger */
pm_iowrite(0x37, pm_ioread(0x37) & (~(1 << 6)));
/* No wait for STPGNT# in ACPI Sx state */
pm_iowrite(0x7c, pm_ioread(0x7c) | (1 << 6));
/* Set GPM3 pull-down enable */
value = pm2_ioread(0xf6);
value |= ((1 << 7) | (1 << 3));
pm2_iowrite(0xf6, value);
/* Set GPM9 pull-down enable */
value = pm2_ioread(0xf8);
value |= ((1 << 5) | (1 << 1));
pm2_iowrite(0xf8, value);
}
int __init sbx00_acpi_init(void)
{
register_acpi_resource();
acpi_registers_setup();
acpi_hw_clear_status();
return 0;
}

4
drivers/platform/mips/cpu_hwmon.c
View File

@@ -20,9 +20,9 @@ int loongson3_cpu_temp(int cpu)
u32 reg;
reg = LOONGSON_CHIPTEMP(cpu);
if (loongson_sysconf.cputype == Loongson_3A)
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1)
reg = (reg >> 8) & 0xff;
else if (loongson_sysconf.cputype == Loongson_3B)
else
reg = ((reg >> 8) & 0xff) - 100;
return (int)reg * 1000;