Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (26 commits) arch/tile: prefer "tilepro" as the name of the 32-bit architecture compat: include aio_abi.h for aio_context_t arch/tile: cleanups for tilegx compat mode arch/tile: allocate PCI IRQs later in boot arch/tile: support signal "exception-trace" hook arch/tile: use better definitions of xchg() and cmpxchg() include/linux/compat.h: coding-style fixes tile: add an RTC driver for the Tilera hypervisor arch/tile: finish enabling support for TILE-Gx 64-bit chip compat: fixes to allow working with tile arch arch/tile: update defconfig file to something more useful tile: do_hardwall_trap: do not play with task->sighand tile: replace mm->cpu_vm_mask with mm_cpumask() tile,mn10300: add device parameter to dma_cache_sync() audit: support the "standard" <asm-generic/unistd.h> arch/tile: clarify flush_buffer()/finv_buffer() function names arch/tile: kernel-related cleanups from removing static page size arch/tile: various header improvements for building drivers arch/tile: disable GX prefetcher during cache flush arch/tile: tolerate disabling CONFIG_BLK_DEV_INITRD ...
This commit is contained in:
Linus Torvalds
@@ -43,8 +43,11 @@
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#include <arch/interrupts.h>
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static noinline void force_sig_info_fault(int si_signo, int si_code,
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unsigned long address, int fault_num, struct task_struct *tsk)
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static noinline void force_sig_info_fault(const char *type, int si_signo,
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int si_code, unsigned long address,
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int fault_num,
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struct task_struct *tsk,
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struct pt_regs *regs)
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{
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siginfo_t info;
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@@ -59,6 +62,7 @@ static noinline void force_sig_info_fault(int si_signo, int si_code,
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info.si_code = si_code;
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info.si_addr = (void __user *)address;
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info.si_trapno = fault_num;
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trace_unhandled_signal(type, regs, address, si_signo);
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force_sig_info(si_signo, &info, tsk);
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}
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@@ -71,11 +75,12 @@ SYSCALL_DEFINE2(cmpxchg_badaddr, unsigned long, address,
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struct pt_regs *, regs)
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{
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if (address >= PAGE_OFFSET)
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force_sig_info_fault(SIGSEGV, SEGV_MAPERR, address,
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INT_DTLB_MISS, current);
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force_sig_info_fault("atomic segfault", SIGSEGV, SEGV_MAPERR,
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address, INT_DTLB_MISS, current, regs);
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else
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force_sig_info_fault(SIGBUS, BUS_ADRALN, address,
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INT_UNALIGN_DATA, current);
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force_sig_info_fault("atomic alignment fault", SIGBUS,
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BUS_ADRALN, address,
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INT_UNALIGN_DATA, current, regs);
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/*
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* Adjust pc to point at the actual instruction, which is unusual
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@@ -471,8 +476,8 @@ bad_area_nosemaphore:
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*/
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local_irq_enable();
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force_sig_info_fault(SIGSEGV, si_code, address,
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fault_num, tsk);
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force_sig_info_fault("segfault", SIGSEGV, si_code, address,
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fault_num, tsk, regs);
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return 0;
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}
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@@ -547,7 +552,8 @@ do_sigbus:
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if (is_kernel_mode)
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goto no_context;
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force_sig_info_fault(SIGBUS, BUS_ADRERR, address, fault_num, tsk);
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force_sig_info_fault("bus error", SIGBUS, BUS_ADRERR, address,
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fault_num, tsk, regs);
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return 0;
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}
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@@ -732,6 +738,7 @@ void do_page_fault(struct pt_regs *regs, int fault_num,
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panic("Bad fault number %d in do_page_fault", fault_num);
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}
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#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
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if (EX1_PL(regs->ex1) != USER_PL) {
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struct async_tlb *async;
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switch (fault_num) {
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@@ -775,6 +782,7 @@ void do_page_fault(struct pt_regs *regs, int fault_num,
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return;
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}
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}
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#endif
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handle_page_fault(regs, fault_num, is_page_fault, address, write);
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}
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@@ -801,8 +809,6 @@ static void handle_async_page_fault(struct pt_regs *regs,
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async->address, async->is_write);
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}
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}
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#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
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/*
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* This routine effectively re-issues asynchronous page faults
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@@ -824,6 +830,8 @@ void do_async_page_fault(struct pt_regs *regs)
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handle_async_page_fault(regs, ¤t->thread.sn_async_tlb);
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#endif
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}
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#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
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void vmalloc_sync_all(void)
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{
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187
arch/tile/mm/migrate_64.S
Normal file
187
arch/tile/mm/migrate_64.S
Normal file
@@ -0,0 +1,187 @@
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/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* This routine is a helper for migrating the home of a set of pages to
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* a new cpu. See the documentation in homecache.c for more information.
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <asm/types.h>
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#include <asm/asm-offsets.h>
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#include <hv/hypervisor.h>
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.text
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/*
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* First, some definitions that apply to all the code in the file.
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*/
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/* Locals (caller-save) */
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#define r_tmp r10
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#define r_save_sp r11
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/* What we save where in the stack frame; must include all callee-saves. */
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#define FRAME_SP 8
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#define FRAME_R30 16
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#define FRAME_R31 24
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#define FRAME_R32 32
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#define FRAME_R33 40
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#define FRAME_SIZE 48
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/*
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* On entry:
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*
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* r0 the new context PA to install (moved to r_context)
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* r1 PTE to use for context access (moved to r_access)
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* r2 ASID to use for new context (moved to r_asid)
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* r3 pointer to cpumask with just this cpu set in it (r_my_cpumask)
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*/
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/* Arguments (caller-save) */
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#define r_context_in r0
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#define r_access_in r1
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#define r_asid_in r2
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#define r_my_cpumask r3
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/* Locals (callee-save); must not be more than FRAME_xxx above. */
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#define r_save_ics r30
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#define r_context r31
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#define r_access r32
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#define r_asid r33
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/*
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* Caller-save locals and frame constants are the same as
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* for homecache_migrate_stack_and_flush.
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*/
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STD_ENTRY(flush_and_install_context)
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/*
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* Create a stack frame; we can't touch it once we flush the
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* cache until we install the new page table and flush the TLB.
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*/
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{
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move r_save_sp, sp
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st sp, lr
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addi sp, sp, -FRAME_SIZE
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}
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addi r_tmp, sp, FRAME_SP
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{
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st r_tmp, r_save_sp
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addi r_tmp, sp, FRAME_R30
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}
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{
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st r_tmp, r30
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addi r_tmp, sp, FRAME_R31
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}
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{
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st r_tmp, r31
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addi r_tmp, sp, FRAME_R32
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}
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{
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st r_tmp, r32
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addi r_tmp, sp, FRAME_R33
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}
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st r_tmp, r33
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/* Move some arguments to callee-save registers. */
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{
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move r_context, r_context_in
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move r_access, r_access_in
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}
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move r_asid, r_asid_in
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/* Disable interrupts, since we can't use our stack. */
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{
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mfspr r_save_ics, INTERRUPT_CRITICAL_SECTION
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movei r_tmp, 1
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}
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mtspr INTERRUPT_CRITICAL_SECTION, r_tmp
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/* First, flush our L2 cache. */
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{
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move r0, zero /* cache_pa */
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moveli r1, hw2_last(HV_FLUSH_EVICT_L2) /* cache_control */
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}
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{
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shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
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move r2, r_my_cpumask /* cache_cpumask */
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}
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{
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shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2)
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move r3, zero /* tlb_va */
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}
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{
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move r4, zero /* tlb_length */
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move r5, zero /* tlb_pgsize */
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}
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{
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move r6, zero /* tlb_cpumask */
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move r7, zero /* asids */
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}
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{
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move r8, zero /* asidcount */
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jal hv_flush_remote
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}
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bnez r0, 1f
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/* Now install the new page table. */
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{
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move r0, r_context
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move r1, r_access
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}
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{
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move r2, r_asid
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movei r3, HV_CTX_DIRECTIO
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}
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jal hv_install_context
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bnez r0, 1f
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/* Finally, flush the TLB. */
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{
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movei r0, 0 /* preserve_global */
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jal hv_flush_all
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}
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1: /* Reset interrupts back how they were before. */
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mtspr INTERRUPT_CRITICAL_SECTION, r_save_ics
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/* Restore the callee-saved registers and return. */
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addli lr, sp, FRAME_SIZE
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{
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ld lr, lr
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addli r_tmp, sp, FRAME_R30
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}
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{
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ld r30, r_tmp
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addli r_tmp, sp, FRAME_R31
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}
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{
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ld r31, r_tmp
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addli r_tmp, sp, FRAME_R32
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}
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{
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ld r32, r_tmp
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addli r_tmp, sp, FRAME_R33
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}
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{
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ld r33, r_tmp
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addi sp, sp, FRAME_SIZE
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}
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jrp lr
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STD_ENDPROC(flush_and_install_context)
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