dmaengine: dw: Remove unused internal property
All known devices, which use DT for configuration, support memory-to-memory transfers. So enable it by default. The rest two cases, i.e. Intel Quark and PPC460ex, instantiate DMA driver and use its channels exclusively for hardware, which means there is no available channel for any other purposes anyway. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
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committed by
Vinod Koul

parent
d7dba6be0f
commit
0781657796
@@ -1227,7 +1227,6 @@ int dw_dma_probe(struct dw_dma_chip *chip)
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pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
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/* Fill platform data with the default values */
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pdata->is_memcpy = true;
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pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
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pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
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} else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
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@@ -1340,8 +1339,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
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/* Set capabilities */
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dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
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dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
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if (pdata->is_memcpy)
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dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
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dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
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dw->dma.dev = chip->dev;
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dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
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@@ -17,7 +17,6 @@
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static struct dw_dma_platform_data mrfld_pdata = {
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.nr_channels = 8,
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.is_memcpy = true,
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.is_idma32 = true,
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.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
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.chan_priority = CHAN_PRIORITY_ASCENDING,
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@@ -128,12 +128,6 @@ dw_dma_parse_dt(struct platform_device *pdev)
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pdata->nr_masters = nr_masters;
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pdata->nr_channels = nr_channels;
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/*
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* All known devices, which use DT for configuration, support
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* memory-to-memory transfers. So enable it by default.
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*/
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pdata->is_memcpy = true;
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if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
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pdata->chan_allocation_order = (unsigned char)tmp;
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