lan743x: lan743x: Add PTP support
PTP support includes: Ingress, and egress timestamping. One step timestamping available. PTP clock support. Periodic output support. Signed-off-by: Bryan Whitehead <Bryan.Whitehead@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:

committed by
David S. Miller

parent
217e502b89
commit
07624df1c9
@@ -4,12 +4,17 @@
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#ifndef _LAN743X_H
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#define _LAN743X_H
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#include "lan743x_ptp.h"
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#define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
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#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
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#define DRIVER_NAME "lan743x"
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/* Register Definitions */
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#define ID_REV (0x00)
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#define ID_REV_ID_MASK_ (0xFFFF0000)
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#define ID_REV_ID_LAN7430_ (0x74300000)
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#define ID_REV_ID_LAN7431_ (0x74310000)
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#define ID_REV_IS_VALID_CHIP_ID_(id_rev) \
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(((id_rev) & 0xFFF00000) == 0x74300000)
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#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
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@@ -62,6 +67,21 @@
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#define E2P_DATA (0x044)
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#define GPIO_CFG0 (0x050)
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#define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))
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#define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
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#define GPIO_CFG1 (0x054)
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#define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))
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#define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
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#define GPIO_CFG2 (0x058)
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#define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
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#define GPIO_CFG3 (0x05C)
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#define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))
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#define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
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#define FCT_RX_CTL (0xAC)
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#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
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#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
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@@ -193,7 +213,8 @@
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#define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))
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#define INT_BIT_ALL_TX_ (0x000F0000)
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#define INT_BIT_SW_GP_ BIT(9)
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#define INT_BIT_ALL_OTHER_ (0x00000280)
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#define INT_BIT_1588_ BIT(7)
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#define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_)
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#define INT_BIT_MAS_ BIT(0)
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#define INT_SET (0x784)
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@@ -234,6 +255,71 @@
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#define INT_MOD_CFG6 (0x7D8)
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#define INT_MOD_CFG7 (0x7DC)
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#define PTP_CMD_CTL (0x0A00)
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#define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6)
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#define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5)
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#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
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#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
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#define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)
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#define PTP_CMD_CTL_PTP_DISABLE_ BIT(1)
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#define PTP_CMD_CTL_PTP_RESET_ BIT(0)
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#define PTP_GENERAL_CONFIG (0x0A04)
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
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(0x7 << (1 + ((channel) << 2)))
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1)
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3)
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5)
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#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
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(((value) & 0x7) << (1 + ((channel) << 2)))
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#define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2))
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#define PTP_INT_STS (0x0A08)
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#define PTP_INT_EN_SET (0x0A0C)
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#define PTP_INT_EN_CLR (0x0A10)
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#define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13)
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#define PTP_INT_BIT_TX_TS_ BIT(12)
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#define PTP_INT_BIT_TIMER_B_ BIT(1)
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#define PTP_INT_BIT_TIMER_A_ BIT(0)
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#define PTP_CLOCK_SEC (0x0A14)
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#define PTP_CLOCK_NS (0x0A18)
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#define PTP_CLOCK_SUBNS (0x0A1C)
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#define PTP_CLOCK_RATE_ADJ (0x0A20)
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#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31)
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#define PTP_CLOCK_STEP_ADJ (0x0A2C)
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#define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31)
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#define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
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#define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
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#define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
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#define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
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#define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
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#define PTP_LATENCY (0x0A5C)
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#define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16)
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#define PTP_LATENCY_RX_SET_(rx_latency) \
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(((u32)(rx_latency)) & 0x0000FFFF)
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#define PTP_CAP_INFO (0x0A60)
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#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
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#define PTP_TX_MOD (0x0AA4)
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#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
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#define PTP_TX_MOD2 (0x0AA8)
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#define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
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#define PTP_TX_EGRESS_SEC (0x0AAC)
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#define PTP_TX_EGRESS_NS (0x0AB0)
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#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
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#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
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#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
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#define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
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#define PTP_TX_MSG_HEADER (0x0AB4)
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#define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
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#define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
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#define DMAC_CFG (0xC00)
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#define DMAC_CFG_COAL_EN_ BIT(16)
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#define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
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@@ -542,8 +628,12 @@ struct lan743x_tx_buffer_info;
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#define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
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#define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
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#define TX_TS_FLAG_ONE_STEP_SYNC BIT(1)
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struct lan743x_tx {
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struct lan743x_adapter *adapter;
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u32 ts_flags;
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u32 vector_flags;
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int channel_number;
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@@ -570,6 +660,10 @@ struct lan743x_tx {
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struct sk_buff *overflow_skb;
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};
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void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
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bool enable_timestamping,
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bool enable_onestep_sync);
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/* RX */
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struct lan743x_rx_descriptor;
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struct lan743x_rx_buffer_info;
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@@ -610,6 +704,9 @@ struct lan743x_adapter {
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/* lock, used to prevent concurrent access to data port */
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struct mutex dp_lock;
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struct lan743x_gpio gpio;
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struct lan743x_ptp ptp;
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u8 mac_address[ETH_ALEN];
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struct lan743x_phy phy;
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@@ -660,6 +757,7 @@ struct lan743x_adapter {
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#define TX_DESC_DATA0_IPE_ (0x00200000)
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#define TX_DESC_DATA0_TPE_ (0x00100000)
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#define TX_DESC_DATA0_FCS_ (0x00020000)
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#define TX_DESC_DATA0_TSE_ (0x00010000)
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#define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
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#define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
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#define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
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@@ -673,6 +771,7 @@ struct lan743x_tx_descriptor {
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} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
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#define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
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#define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1)
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#define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)
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#define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3)
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struct lan743x_tx_buffer_info {
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