[ARM] Orion: share GPIO IRQ handling code
Split off Orion GPIO IRQ handling code into plat-orion/. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek
committed by
Nicolas Pitre
Nicolas Pitre
parent
9569dae75f
commit
07332318f3
@@ -10,6 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/bitops.h>
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@@ -237,3 +238,178 @@ void orion_gpio_set_blink(unsigned pin, int blink)
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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EXPORT_SYMBOL(orion_gpio_set_blink);
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/*****************************************************************************
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* Orion GPIO IRQ
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*
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* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
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* value of the line or the opposite value.
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*
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* Level IRQ handlers: DATA_IN is used directly as cause register.
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* Interrupt are masked by LEVEL_MASK registers.
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
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* Interrupt are masked by EDGE_MASK registers.
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps
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* the polarity to catch the next line transaction.
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* This is a race condition that might not perfectly
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* work on some use cases.
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*
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* Every eight GPIO lines are grouped (OR'ed) before going up to main
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* cause register.
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*
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* EDGE cause mask
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* data-in /--------| |-----| |----\
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* -----| |----- ---- to main cause reg
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* X \----------------| |----/
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* polarity LEVEL mask
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*
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****************************************************************************/
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static void gpio_irq_edge_ack(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
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}
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static void gpio_irq_edge_mask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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u32 u;
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u = readl(GPIO_EDGE_MASK(pin));
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u &= ~(1 << (pin & 31));
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writel(u, GPIO_EDGE_MASK(pin));
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}
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static void gpio_irq_edge_unmask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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u32 u;
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u = readl(GPIO_EDGE_MASK(pin));
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u |= 1 << (pin & 31);
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writel(u, GPIO_EDGE_MASK(pin));
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}
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static void gpio_irq_level_mask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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u32 u;
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u = readl(GPIO_LEVEL_MASK(pin));
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u &= ~(1 << (pin & 31));
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writel(u, GPIO_LEVEL_MASK(pin));
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}
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static void gpio_irq_level_unmask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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u32 u;
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u = readl(GPIO_LEVEL_MASK(pin));
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u |= 1 << (pin & 31);
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writel(u, GPIO_LEVEL_MASK(pin));
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}
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static int gpio_irq_set_type(u32 irq, u32 type)
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{
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int pin = irq_to_gpio(irq);
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struct irq_desc *desc;
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u32 u;
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u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
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if (!u) {
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printk(KERN_ERR "orion gpio_irq_set_type failed "
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"(irq %d, pin %d).\n", irq, pin);
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return -EINVAL;
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}
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desc = irq_desc + irq;
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/*
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* Set edge/level type.
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*/
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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desc->chip = &orion_gpio_irq_edge_chip;
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} else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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desc->chip = &orion_gpio_irq_level_chip;
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} else {
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printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
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return -EINVAL;
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}
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/*
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* Configure interrupt polarity.
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*/
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if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
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u = readl(GPIO_IN_POL(pin));
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u &= ~(1 << (pin & 31));
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writel(u, GPIO_IN_POL(pin));
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} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
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u = readl(GPIO_IN_POL(pin));
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u |= 1 << (pin & 31);
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writel(u, GPIO_IN_POL(pin));
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} else if (type == IRQ_TYPE_EDGE_BOTH) {
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u32 v;
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v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
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/*
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* set initial polarity based on current input level
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*/
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u = readl(GPIO_IN_POL(pin));
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if (v & (1 << (pin & 31)))
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u |= 1 << (pin & 31); /* falling */
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else
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u &= ~(1 << (pin & 31)); /* rising */
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writel(u, GPIO_IN_POL(pin));
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}
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desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
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return 0;
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}
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struct irq_chip orion_gpio_irq_edge_chip = {
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.name = "orion_gpio_irq_edge",
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.ack = gpio_irq_edge_ack,
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.mask = gpio_irq_edge_mask,
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.unmask = gpio_irq_edge_unmask,
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.set_type = gpio_irq_set_type,
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};
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struct irq_chip orion_gpio_irq_level_chip = {
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.name = "orion_gpio_irq_level",
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.mask = gpio_irq_level_mask,
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.mask_ack = gpio_irq_level_mask,
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.unmask = gpio_irq_level_unmask,
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.set_type = gpio_irq_set_type,
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};
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void orion_gpio_irq_handler(int pinoff)
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{
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u32 cause;
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int pin;
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cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
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cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
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for (pin = pinoff; pin < pinoff + 8; pin++) {
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int irq = gpio_to_irq(pin);
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struct irq_desc *desc = irq_desc + irq;
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if (!(cause & (1 << (pin & 31))))
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continue;
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if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
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/* Swap polarity (race with GPIO line) */
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u32 polarity;
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polarity = readl(GPIO_IN_POL(pin));
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polarity ^= 1 << (pin & 31);
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writel(polarity, GPIO_IN_POL(pin));
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}
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desc_handle_irq(irq, desc);
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}
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}
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