Merge tag 'powerpc-4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
"Highlights:
- Major rework of Book3S 64-bit exception vectors (Nicholas Piggin)
- Use gas sections for arranging exception vectors et. al.
- Large set of TM cleanups and selftests (Cyril Bur)
- Enable transactional memory (TM) lazily for userspace (Cyril Bur)
- Support for XZ compression in the zImage wrapper (Oliver
O'Halloran)
- Add support for bpf constant blinding (Naveen N. Rao)
- Beginnings of upstream support for PA Semi Nemo motherboards
(Darren Stevens)
Fixes:
- Ensure .mem(init|exit).text are within _stext/_etext (Michael
Ellerman)
- xmon: Don't use ld on 32-bit (Michael Ellerman)
- vdso64: Use double word compare on pointers (Anton Blanchard)
- powerpc/nvram: Fix an incorrect partition merge (Pan Xinhui)
- powerpc: Fix usage of _PAGE_RO in hugepage (Christophe Leroy)
- powerpc/mm: Update FORCE_MAX_ZONEORDER range to allow hugetlb w/4K
(Aneesh Kumar K.V)
- Fix memory leak in queue_hotplug_event() error path (Andrew
Donnellan)
- Replay hypervisor maintenance interrupt first (Nicholas Piggin)
Various performance optimisations (Anton Blanchard):
- Align hot loops of memset() and backwards_memcpy()
- During context switch, check before setting mm_cpumask
- Remove static branch prediction in atomic{, 64}_add_unless
- Only disable HAVE_EFFICIENT_UNALIGNED_ACCESS on POWER7 little
endian
- Set default CPU type to POWER8 for little endian builds
Cleanups & features:
- Sparse fixes/cleanups (Daniel Axtens)
- Preserve CFAR value on SLB miss caused by access to bogus address
(Paul Mackerras)
- Radix MMU fixups for POWER9 (Aneesh Kumar K.V)
- Support for setting used_(vsr|vr|spe) in sigreturn path (for CRIU)
(Simon Guo)
- Optimise syscall entry for virtual, relocatable case (Nicholas
Piggin)
- Optimise MSR handling in exception handling (Nicholas Piggin)
- Support for kexec with Radix MMU (Benjamin Herrenschmidt)
- powernv EEH fixes (Russell Currey)
- Suprise PCI hotplug support for powernv (Gavin Shan)
- Endian/sparse fixes for powernv PCI (Gavin Shan)
- Defconfig updates (Anton Blanchard)
- KVM: PPC: Book3S HV: Migrate pinned pages out of CMA (Balbir Singh)
- cxl: Flush PSL cache before resetting the adapter (Frederic Barrat)
- cxl: replace loop with for_each_child_of_node(), remove unneeded
of_node_put() (Andrew Donnellan)
- Fix HV facility unavailable to use correct handler (Nicholas
Piggin)
- Remove unnecessary syscall trampoline (Nicholas Piggin)
- fadump: Fix build break when CONFIG_PROC_VMCORE=n (Michael
Ellerman)
- Quieten EEH message when no adapters are found (Anton Blanchard)
- powernv: Add PHB register dump debugfs handle (Russell Currey)
- Use kprobe blacklist for exception handlers & asm functions
(Nicholas Piggin)
- Document the syscall ABI (Nicholas Piggin)
- MAINTAINERS: Update cxl maintainers (Michael Neuling)
- powerpc: Remove all usages of NO_IRQ (Michael Ellerman)
Minor cleanups:
- Andrew Donnellan, Christophe Leroy, Colin Ian King, Cyril Bur,
Frederic Barrat, Pan Xinhui, PrasannaKumar Muralidharan, Rui Teng,
Simon Guo"
* tag 'powerpc-4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (156 commits)
powerpc/bpf: Add support for bpf constant blinding
powerpc/bpf: Implement support for tail calls
powerpc/bpf: Introduce accessors for using the tmp local stack space
powerpc/fadump: Fix build break when CONFIG_PROC_VMCORE=n
powerpc: tm: Enable transactional memory (TM) lazily for userspace
powerpc/tm: Add TM Unavailable Exception
powerpc: Remove do_load_up_transact_{fpu,altivec}
powerpc: tm: Rename transct_(*) to ck(\1)_state
powerpc: tm: Always use fp_state and vr_state to store live registers
selftests/powerpc: Add checks for transactional VSXs in signal contexts
selftests/powerpc: Add checks for transactional VMXs in signal contexts
selftests/powerpc: Add checks for transactional FPUs in signal contexts
selftests/powerpc: Add checks for transactional GPRs in signal contexts
selftests/powerpc: Check that signals always get delivered
selftests/powerpc: Add TM tcheck helpers in C
selftests/powerpc: Allow tests to extend their kill timeout
selftests/powerpc: Introduce GPR asm helper header file
selftests/powerpc: Move VMX stack frame macros to header file
selftests/powerpc: Rework FPU stack placement macros and move to header file
selftests/powerpc: Check for VSX preservation across userspace preemption
...
This commit is contained in:
Linus Torvalds
@@ -6,6 +6,8 @@
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*/
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#define _PAGE_BIT_SWAP_TYPE 0
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#define _PAGE_RO 0
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#define _PAGE_EXEC 0x00001 /* execute permission */
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#define _PAGE_WRITE 0x00002 /* write access allowed */
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#define _PAGE_READ 0x00004 /* read access allowed */
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@@ -565,10 +567,11 @@ static inline bool check_pte_access(unsigned long access, unsigned long ptev)
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* Generic functions with hash/radix callbacks
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*/
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static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
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static inline void __ptep_set_access_flags(struct mm_struct *mm,
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pte_t *ptep, pte_t entry)
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{
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if (radix_enabled())
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return radix__ptep_set_access_flags(ptep, entry);
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return radix__ptep_set_access_flags(mm, ptep, entry);
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return hash__ptep_set_access_flags(ptep, entry);
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}
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@@ -11,6 +11,11 @@
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#include <asm/book3s/64/radix-4k.h>
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#endif
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#ifndef __ASSEMBLY__
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#include <asm/book3s/64/tlbflush-radix.h>
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#include <asm/cpu_has_feature.h>
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#endif
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/* An empty PTE can still have a R or C writeback */
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#define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
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@@ -105,11 +110,8 @@
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#define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
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#define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
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static inline unsigned long radix__pte_update(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, unsigned long clr,
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unsigned long set,
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int huge)
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static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
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unsigned long set)
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{
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pte_t pte;
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unsigned long old_pte, new_pte;
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@@ -121,9 +123,39 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm,
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} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
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/* We already do a sync in cmpxchg, is ptesync needed ?*/
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return old_pte;
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}
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static inline unsigned long radix__pte_update(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, unsigned long clr,
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unsigned long set,
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int huge)
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{
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unsigned long old_pte;
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if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
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unsigned long new_pte;
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old_pte = __radix_pte_update(ptep, ~0, 0);
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asm volatile("ptesync" : : : "memory");
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/*
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* new value of pte
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*/
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new_pte = (old_pte | set) & ~clr;
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/*
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* For now let's do heavy pid flush
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* radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize);
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*/
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radix__flush_tlb_mm(mm);
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__radix_pte_update(ptep, 0, new_pte);
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} else
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old_pte = __radix_pte_update(ptep, clr, set);
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asm volatile("ptesync" : : : "memory");
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/* huge pages use the old page table lock */
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if (!huge)
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assert_pte_locked(mm, addr);
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@@ -134,20 +166,33 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm,
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* Set the dirty and/or accessed bits atomically in a linux PTE, this
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* function doesn't need to invalidate tlb.
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*/
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static inline void radix__ptep_set_access_flags(pte_t *ptep, pte_t entry)
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static inline void radix__ptep_set_access_flags(struct mm_struct *mm,
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pte_t *ptep, pte_t entry)
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{
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pte_t pte;
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unsigned long old_pte, new_pte;
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unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
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_PAGE_RW | _PAGE_EXEC);
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do {
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pte = READ_ONCE(*ptep);
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old_pte = pte_val(pte);
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if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
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unsigned long old_pte, new_pte;
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old_pte = __radix_pte_update(ptep, ~0, 0);
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asm volatile("ptesync" : : : "memory");
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/*
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* new value of pte
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*/
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new_pte = old_pte | set;
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} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
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/*
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* For now let's do heavy pid flush
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* radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize);
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*/
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radix__flush_tlb_mm(mm);
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/* We already do a sync in cmpxchg, is ptesync needed ?*/
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__radix_pte_update(ptep, 0, new_pte);
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} else
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__radix_pte_update(ptep, 0, set);
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asm volatile("ptesync" : : : "memory");
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}
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@@ -233,14 +278,19 @@ static inline unsigned long radix__get_tree_size(void)
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{
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unsigned long rts_field;
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/*
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* we support 52 bits, hence 52-31 = 21, 0b10101
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* We support 52 bits, hence:
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* DD1 52-28 = 24, 0b11000
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* Others 52-31 = 21, 0b10101
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* RTS encoding details
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* bits 0 - 3 of rts -> bits 6 - 8 unsigned long
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* bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
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*/
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rts_field = (0x5UL << 5); /* 6 - 8 bits */
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rts_field |= (0x2UL << 61);
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if (cpu_has_feature(CPU_FTR_POWER9_DD1))
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rts_field = (0x3UL << 61);
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else {
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rts_field = (0x5UL << 5); /* 6 - 8 bits */
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rts_field |= (0x2UL << 61);
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}
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return rts_field;
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}
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#endif /* __ASSEMBLY__ */
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@@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmad
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extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
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unsigned long page_size);
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extern void radix__flush_tlb_lpid(unsigned long lpid);
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extern void radix__flush_tlb_all(void);
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#endif
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