Merge tag 'char-misc-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc updates from Greg KH: "Here is the big set of char/misc driver patches for 4.17-rc1. There are a lot of little things in here, nothing huge, but all important to the different hardware types involved: - thunderbolt driver updates - parport updates (people still care...) - nvmem driver updates - mei updates (as always) - hwtracing driver updates - hyperv driver updates - extcon driver updates - ... and a handful of even smaller driver subsystem and individual driver updates All of these have been in linux-next with no reported issues" * tag 'char-misc-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (149 commits) hwtracing: Add HW tracing support menu intel_th: Add ACPI glue layer intel_th: Allow forcing host mode through drvdata intel_th: Pick up irq number from resources intel_th: Don't touch switch routing in host mode intel_th: Use correct method of finding hub intel_th: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate stm class: Make dummy's master/channel ranges configurable stm class: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate MAINTAINERS: Bestow upon myself the care for drivers/hwtracing hv: add SPDX license id to Kconfig hv: add SPDX license to trace Drivers: hv: vmbus: do not mark HV_PCIE as perf_device Drivers: hv: vmbus: respect what we get from hv_get_synint_state() /dev/mem: Avoid overwriting "err" in read_mem() eeprom: at24: use SPDX identifier instead of GPL boiler-plate eeprom: at24: simplify the i2c functionality checking eeprom: at24: fix a line break eeprom: at24: tweak newlines eeprom: at24: refactor at24_probe() ...
This commit is contained in:
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Samsung micro-USB 11-pin connector
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==================================
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Samsung micro-USB 11-pin connector is an extension of micro-USB connector.
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It is present in multiple Samsung mobile devices.
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It has additional pins to route MHL traffic simultanously with USB.
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The bindings are superset of usb-connector bindings for micro-USB connector[1].
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Required properties:
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- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector",
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- type: must be "micro".
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Required nodes:
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- any data bus to the connector should be modeled using the OF graph bindings
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specified in bindings/graph.txt, unless the bus is between parent node and
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the connector. Since single connector can have multpile data buses every bus
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has assigned OF graph port number as follows:
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0: High Speed (HS),
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3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
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[1]: bindings/connector/usb-connector.txt
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Example
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-------
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Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines
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connected to HDMI-MHL bridge (sii8620):
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muic-max77843@66 {
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...
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usb_con: connector {
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compatible = "samsung,usb-connector-11pin", "usb-b-connector";
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label = "micro-USB";
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type = "micro";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@3 {
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reg = <3>;
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usb_con_mhl: endpoint {
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remote-endpoint = <&sii8620_mhl>;
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};
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};
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};
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};
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};
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USB Connector
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=============
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USB connector node represents physical USB connector. It should be
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a child of USB interface controller.
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Required properties:
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- compatible: describes type of the connector, must be one of:
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"usb-a-connector",
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"usb-b-connector",
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"usb-c-connector".
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Optional properties:
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- label: symbolic name for the connector,
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- type: size of the connector, should be specified in case of USB-A, USB-B
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non-fullsize connectors: "mini", "micro".
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Required nodes:
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- any data bus to the connector should be modeled using the OF graph bindings
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specified in bindings/graph.txt, unless the bus is between parent node and
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the connector. Since single connector can have multpile data buses every bus
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has assigned OF graph port number as follows:
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0: High Speed (HS), present in all connectors,
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1: Super Speed (SS), present in SS capable connectors,
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2: Sideband use (SBU), present in USB-C.
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Examples
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--------
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1. Micro-USB connector with HS lines routed via controller (MUIC):
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muic-max77843@66 {
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...
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usb_con: connector {
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compatible = "usb-b-connector";
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label = "micro-USB";
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type = "micro";
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};
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};
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2. USB-C connector attached to CC controller (s2mm005), HS lines routed
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to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
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DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
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ccic: s2mm005@33 {
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...
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usb_con: connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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usb_con_hs: endpoint {
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remote-endpoint = <&max77865_usbc_hs>;
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};
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};
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port@1 {
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reg = <1>;
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usb_con_ss: endpoint {
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remote-endpoint = <&usbdrd_phy_ss>;
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};
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};
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port@2 {
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reg = <2>;
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usb_con_sbu: endpoint {
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remote-endpoint = <&dp_aux>;
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};
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};
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};
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};
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};
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151
Documentation/devicetree/bindings/fsi/fsi.txt
Normal file
151
Documentation/devicetree/bindings/fsi/fsi.txt
Normal file
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FSI bus & engine generic device tree bindings
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=============================================
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The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
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engines within those slaves. However, we have a facility to match devicetree
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nodes to probed engines. This allows for fsi engines to expose non-probeable
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busses, which are then exposed by the device tree. For example, an FSI engine
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that is an I2C master - the I2C bus can be described by the device tree under
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the engine's device tree node.
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FSI masters may require their own DT nodes (to describe the master HW itself);
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that requirement is defined by the master's implementation, and is described by
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the fsi-master-* binding specifications.
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Under the masters' nodes, we can describe the bus topology using nodes to
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represent the FSI slaves and their slave engines. As a basic outline:
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fsi-master {
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/* top-level of FSI bus topology, bound to an FSI master driver and
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* exposes an FSI bus */
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fsi-slave@<link,id> {
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/* this node defines the FSI slave device, and is handled
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* entirely with FSI core code */
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fsi-slave-engine@<addr> {
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/* this node defines the engine endpoint & address range, which
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* is bound to the relevant fsi device driver */
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...
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};
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fsi-slave-engine@<addr> {
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...
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};
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};
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};
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Note that since the bus is probe-able, some (or all) of the topology may
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not be described; this binding only provides an optional facility for
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adding subordinate device tree nodes as children of FSI engines.
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FSI masters
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-----------
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FSI master nodes declare themselves as such with the "fsi-master" compatible
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value. It's likely that an implementation-specific compatible value will
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be needed as well, for example:
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compatible = "fsi-master-gpio", "fsi-master";
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Since the master nodes describe the top-level of the FSI topology, they also
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need to declare the FSI-standard addressing scheme. This requires two cells for
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addresses (link index and slave ID), and no size:
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#address-cells = <2>;
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#size-cells = <0>;
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An optional boolean property can be added to indicate that a particular master
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should not scan for connected devices at initialization time. This is
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necessary in cases where a scan could cause arbitration issues with other
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masters that may be present on the bus.
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no-scan-on-init;
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FSI slaves
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----------
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Slaves are identified by a (link-index, slave-id) pair, so require two cells
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for an address identifier. Since these are not a range, no size cells are
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required. For an example, a slave on link 1, with ID 2, could be represented
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as:
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cfam@1,2 {
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reg = <1 2>;
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[...];
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}
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Each slave provides an address-space, under which the engines are accessible.
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That address space has a maximum of 23 bits, so we use one cell to represent
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addresses and sizes in the slave address space:
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#address-cells = <1>;
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#size-cells = <1>;
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FSI engines (devices)
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---------------------
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Engines are identified by their address under the slaves' address spaces. We
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use a single cell for address and size. Engine nodes represent the endpoint
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FSI device, and are passed to those FSI device drivers' ->probe() functions.
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For example, for a slave using a single 0x400-byte page starting at address
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0xc00:
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engine@c00 {
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reg = <0xc00 0x400>;
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};
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Full example
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------------
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Here's an example that illustrates:
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- an FSI master
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- connected to an FSI slave
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- that contains an engine that is an I2C master
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- connected to an I2C EEPROM
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The FSI master may be connected to additional slaves, and slaves may have
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additional engines, but they don't necessarily need to be describe in the
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device tree if no extra platform information is required.
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/* The GPIO-based FSI master node, describing the top level of the
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* FSI bus
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*/
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gpio-fsi {
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compatible = "fsi-master-gpio", "fsi-master";
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#address-cells = <2>;
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#size-cells = <0>;
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/* A FSI slave (aka. CFAM) at link 0, ID 0. */
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cfam@0,0 {
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reg = <0 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* FSI engine at 0xc00, using a single page. In this example,
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* it's an I2C master controller, so subnodes describe the
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* I2C bus.
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*/
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i2c-controller@c00 {
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reg = <0xc00 0x400>;
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/* Engine-specific data. In this case, we're describing an
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* I2C bus, so we're conforming to the generic I2C binding
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*/
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compatible = "some-vendor,fsi-i2c-controller";
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#address-cells = <1>;
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#size-cells = <1>;
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/* I2C endpoint device: an Atmel EEPROM */
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eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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pagesize = <64>;
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};
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};
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};
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};
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@@ -109,9 +109,50 @@ lpc: lpc@1e789000 {
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};
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};
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BMC Node Children
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==================
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Host Node Children
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==================
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LPC Host Interface Controller
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-------------------
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The LPC Host Interface Controller manages functions exposed to the host such as
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LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
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management and bus snoop configuration.
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Required properties:
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- compatible: One of:
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"aspeed,ast2400-lpc-ctrl";
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"aspeed,ast2500-lpc-ctrl";
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- reg: contains offset/length values of the host interface controller
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memory regions
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- clocks: contains a phandle to the syscon node describing the clocks.
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There should then be one cell representing the clock to use
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- memory-region: A phandle to a reserved_memory region to be used for the LPC
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to AHB mapping
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- flash: A phandle to the SPI flash controller containing the flash to
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be exposed over the LPC to AHB mapping
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Example:
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lpc-host@80 {
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lpc_ctrl: lpc-ctrl@0 {
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compatible = "aspeed,ast2500-lpc-ctrl";
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reg = <0x0 0x80>;
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clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
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memory-region = <&flash_memory>;
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flash = <&spi>;
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};
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};
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LPC Host Controller
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-------------------
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@@ -11,17 +11,32 @@ Required properties:
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"fsl,imx6ul-ocotp" (i.MX6UL),
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"fsl,imx7d-ocotp" (i.MX7D/S),
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followed by "syscon".
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- #address-cells : Should be 1
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- #size-cells : Should be 1
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- reg: Should contain the register base and length.
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- clocks: Should contain a phandle pointing to the gated peripheral clock.
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Optional properties:
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- read-only: disable write access
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Example:
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Optional Child nodes:
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- Data cells of ocotp:
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Detailed bindings are described in bindings/nvmem/nvmem.txt
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Example:
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ocotp: ocotp@21bc000 {
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compatible = "fsl,imx6q-ocotp", "syscon";
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,imx6sx-ocotp", "syscon";
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reg = <0x021bc000 0x4000>;
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clocks = <&clks IMX6QDL_CLK_IIM>;
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read-only;
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clocks = <&clks IMX6SX_CLK_OCOTP>;
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tempmon_calib: calib@38 {
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reg = <0x38 4>;
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};
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tempmon_temp_grade: temp-grade@20 {
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reg = <0x20 4>;
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};
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};
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@@ -1,5 +1,5 @@
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Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
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Secure Non-Volatile Storage.
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and i.MX7 Secure Non-Volatile Storage.
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This DT node should be represented as a sub-node of a "syscon",
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"simple-mfd" node.
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@@ -8,6 +8,7 @@ Required properties:
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- compatible: should be one of the fallowing variants:
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"fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
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"fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL
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"fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S
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Example:
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snvs: snvs@020cc000 {
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Reference in New Issue
Block a user