Merge tag 'mediatek-drm-next-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
Mediatek DRM Next for Linux 5.10 1. Move Mediatek HDMI PHY driver from DRM folder to PHY folder 2. Convert mtk-dpi to drm_bridge API 3. Disable tmds on mt2701 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200914231227.30500-1-chunkuang.hu@kernel.org
This commit is contained in:
Dave Airlie
@@ -24,6 +24,6 @@ config DRM_MEDIATEK_HDMI
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tristate "DRM HDMI Support for Mediatek SoCs"
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depends on DRM_MEDIATEK
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select SND_SOC_HDMI_CODEC if SND_SOC
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select GENERIC_PHY
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select PHY_MTK_HDMI
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help
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DRM/KMS HDMI driver for Mediatek SoCs
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@@ -19,9 +19,6 @@ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
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mediatek-drm-hdmi-objs := mtk_cec.o \
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mtk_hdmi.o \
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mtk_hdmi_ddc.o \
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mtk_mt2701_hdmi_phy.o \
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mtk_mt8173_hdmi_phy.o \
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mtk_hdmi_phy.o
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mtk_hdmi_ddc.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
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@@ -64,7 +64,8 @@ enum mtk_dpi_out_color_format {
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struct mtk_dpi {
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struct mtk_ddp_comp ddp_comp;
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struct drm_encoder encoder;
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struct drm_bridge *bridge;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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void __iomem *regs;
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struct device *dev;
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struct clk *engine_clk;
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@@ -83,9 +84,9 @@ struct mtk_dpi {
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int refcount;
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};
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static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e)
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static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
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{
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return container_of(e, struct mtk_dpi, encoder);
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return container_of(b, struct mtk_dpi, bridge);
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}
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enum mtk_dpi_polarity {
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@@ -521,50 +522,53 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
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return 0;
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}
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static bool mtk_dpi_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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static void mtk_dpi_encoder_destroy(struct drm_encoder *encoder)
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{
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return true;
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drm_encoder_cleanup(encoder);
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}
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static void mtk_dpi_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = {
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.destroy = mtk_dpi_encoder_destroy,
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};
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static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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return drm_bridge_attach(bridge->encoder, dpi->next_bridge,
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&dpi->bridge, flags);
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}
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static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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drm_mode_copy(&dpi->mode, adjusted_mode);
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}
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static void mtk_dpi_encoder_disable(struct drm_encoder *encoder)
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static void mtk_dpi_bridge_disable(struct drm_bridge *bridge)
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{
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struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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mtk_dpi_power_off(dpi);
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}
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static void mtk_dpi_encoder_enable(struct drm_encoder *encoder)
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static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
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{
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struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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mtk_dpi_power_on(dpi);
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mtk_dpi_set_display_mode(dpi, &dpi->mode);
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}
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static int mtk_dpi_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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return 0;
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}
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static const struct drm_encoder_helper_funcs mtk_dpi_encoder_helper_funcs = {
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.mode_fixup = mtk_dpi_encoder_mode_fixup,
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.mode_set = mtk_dpi_encoder_mode_set,
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.disable = mtk_dpi_encoder_disable,
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.enable = mtk_dpi_encoder_enable,
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.atomic_check = mtk_dpi_atomic_check,
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static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
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.attach = mtk_dpi_bridge_attach,
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.mode_set = mtk_dpi_bridge_mode_set,
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.disable = mtk_dpi_bridge_disable,
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.enable = mtk_dpi_bridge_enable,
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};
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static void mtk_dpi_start(struct mtk_ddp_comp *comp)
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@@ -605,12 +609,10 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
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dev_err(dev, "Failed to initialize decoder: %d\n", ret);
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goto err_unregister;
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}
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drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
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/* Currently DPI0 is fixed to be driven by OVL1 */
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dpi->encoder.possible_crtcs = BIT(1);
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dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp);
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ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0);
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ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 0);
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if (ret) {
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dev_err(dev, "Failed to attach bridge: %d\n", ret);
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goto err_cleanup;
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@@ -770,11 +772,11 @@ static int mtk_dpi_probe(struct platform_device *pdev)
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}
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ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
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NULL, &dpi->bridge);
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NULL, &dpi->next_bridge);
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if (ret)
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return ret;
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dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge->of_node);
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dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node);
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comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
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if (comp_id < 0) {
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@@ -791,8 +793,15 @@ static int mtk_dpi_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, dpi);
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dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
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dpi->bridge.of_node = dev->of_node;
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dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
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drm_bridge_add(&dpi->bridge);
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ret = component_add(dev, &mtk_dpi_component_ops);
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if (ret) {
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drm_bridge_remove(&dpi->bridge);
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dev_err(dev, "Failed to add component: %d\n", ret);
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return ret;
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}
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@@ -802,7 +811,10 @@ static int mtk_dpi_probe(struct platform_device *pdev)
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static int mtk_dpi_remove(struct platform_device *pdev)
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{
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struct mtk_dpi *dpi = platform_get_drvdata(pdev);
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component_del(&pdev->dev, &mtk_dpi_component_ops);
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drm_bridge_remove(&dpi->bridge);
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return 0;
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}
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@@ -13,6 +13,8 @@
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include <drm/drm_print.h>
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#include "mtk_drm_drv.h"
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#include "mtk_drm_plane.h"
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#include "mtk_drm_ddp_comp.h"
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@@ -412,6 +414,22 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
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[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
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};
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static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp,
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const enum mtk_ddp_comp_id *path,
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unsigned int path_len)
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{
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unsigned int i;
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if (path == NULL)
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return false;
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for (i = 0U; i < path_len; i++)
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if (ddp_comp.id == path[i])
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return true;
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return false;
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}
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int mtk_ddp_comp_get_id(struct device_node *node,
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enum mtk_ddp_comp_type comp_type)
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{
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@@ -427,6 +445,26 @@ int mtk_ddp_comp_get_id(struct device_node *node,
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return -EINVAL;
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}
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unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
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struct mtk_ddp_comp ddp_comp)
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{
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struct mtk_drm_private *private = drm->dev_private;
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unsigned int ret = 0;
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if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->main_path, private->data->main_len))
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ret = BIT(0);
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else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->ext_path,
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private->data->ext_len))
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ret = BIT(1);
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else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->third_path,
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private->data->third_len))
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ret = BIT(2);
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else
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DRM_INFO("Failed to find comp in ddp table\n");
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return ret;
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}
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int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
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struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
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const struct mtk_ddp_comp_funcs *funcs)
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@@ -202,6 +202,8 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
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int mtk_ddp_comp_get_id(struct device_node *node,
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enum mtk_ddp_comp_type comp_type);
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unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
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struct mtk_ddp_comp ddp_comp);
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int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
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struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
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const struct mtk_ddp_comp_funcs *funcs);
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@@ -74,6 +74,19 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
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DDP_COMPONENT_DPI0,
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};
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static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
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DDP_COMPONENT_OVL0,
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DDP_COMPONENT_RDMA0,
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DDP_COMPONENT_COLOR0,
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DDP_COMPONENT_BLS,
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DDP_COMPONENT_DPI0,
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};
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static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
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DDP_COMPONENT_RDMA1,
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DDP_COMPONENT_DSI0,
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};
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static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
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DDP_COMPONENT_OVL0,
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DDP_COMPONENT_COLOR0,
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@@ -127,6 +140,14 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
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.shadow_register = true,
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};
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static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
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.main_path = mt7623_mtk_ddp_main,
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.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
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.ext_path = mt7623_mtk_ddp_ext,
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.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
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.shadow_register = true,
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};
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static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
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.main_path = mt2712_mtk_ddp_main,
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.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
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@@ -422,6 +443,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
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static const struct of_device_id mtk_drm_of_ids[] = {
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{ .compatible = "mediatek,mt2701-mmsys",
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.data = &mt2701_mmsys_driver_data},
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{ .compatible = "mediatek,mt7623-mmsys",
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.data = &mt7623_mmsys_driver_data},
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{ .compatible = "mediatek,mt2712-mmsys",
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.data = &mt2712_mmsys_driver_data},
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{ .compatible = "mediatek,mt8173-mmsys",
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@@ -970,11 +970,7 @@ static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
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return ret;
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}
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/*
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* Currently display data paths are statically assigned to a crtc each.
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* crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
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*/
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dsi->encoder.possible_crtcs = 1;
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dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp);
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ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
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DRM_BRIDGE_ATTACH_NO_CONNECTOR);
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@@ -12,6 +12,7 @@
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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#include <linux/of.h>
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@@ -145,11 +146,16 @@ struct hdmi_audio_param {
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struct hdmi_codec_params codec_params;
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};
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struct mtk_hdmi_conf {
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bool tz_disabled;
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};
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struct mtk_hdmi {
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct drm_connector conn;
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struct device *dev;
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const struct mtk_hdmi_conf *conf;
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struct phy *phy;
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struct device *cec_dev;
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struct i2c_adapter *ddc_adpt;
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@@ -234,7 +240,6 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
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static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
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{
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struct arm_smccc_res res;
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struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
|
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|
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/*
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* MT8173 HDMI hardware has an output control bit to enable/disable HDMI
|
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@@ -242,7 +247,7 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
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* The ARM trusted firmware provides an API for the HDMI driver to set
|
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* this control bit to enable HDMI output in supervisor mode.
|
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*/
|
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if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
|
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if (hdmi->conf && hdmi->conf->tz_disabled)
|
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regmap_update_bits(hdmi->sys_regmap,
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hdmi->sys_offset + HDMI_SYS_CFG20,
|
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0x80008005, enable ? 0x80000005 : 0x8000);
|
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@@ -1723,6 +1728,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
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return -ENOMEM;
|
||||
|
||||
hdmi->dev = dev;
|
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hdmi->conf = of_device_get_match_data(dev);
|
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|
||||
ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
|
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if (ret)
|
||||
@@ -1803,8 +1809,16 @@ static int mtk_hdmi_resume(struct device *dev)
|
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static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
|
||||
mtk_hdmi_suspend, mtk_hdmi_resume);
|
||||
|
||||
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
|
||||
.tz_disabled = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
|
||||
{ .compatible = "mediatek,mt8173-hdmi", },
|
||||
{ .compatible = "mediatek,mt2701-hdmi",
|
||||
.data = &mtk_hdmi_conf_mt2701,
|
||||
},
|
||||
{ .compatible = "mediatek,mt8173-hdmi",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
@@ -1819,7 +1833,6 @@ static struct platform_driver mtk_hdmi_driver = {
|
||||
};
|
||||
|
||||
static struct platform_driver * const mtk_hdmi_drivers[] = {
|
||||
&mtk_hdmi_phy_driver,
|
||||
&mtk_hdmi_ddc_driver,
|
||||
&mtk_cec_driver,
|
||||
&mtk_hdmi_driver,
|
||||
|
||||
@@ -5,7 +5,6 @@
|
||||
*/
|
||||
#ifndef _MTK_HDMI_CTRL_H
|
||||
#define _MTK_HDMI_CTRL_H
|
||||
#include "mtk_hdmi_phy.h"
|
||||
|
||||
struct platform_driver;
|
||||
|
||||
|
||||
@@ -1,210 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Jie Qiu <jie.qiu@mediatek.com>
|
||||
*/
|
||||
|
||||
#include "mtk_hdmi_phy.h"
|
||||
|
||||
static int mtk_hdmi_phy_power_on(struct phy *phy);
|
||||
static int mtk_hdmi_phy_power_off(struct phy *phy);
|
||||
|
||||
static const struct phy_ops mtk_hdmi_phy_dev_ops = {
|
||||
.power_on = mtk_hdmi_phy_power_on,
|
||||
.power_off = mtk_hdmi_phy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 bits)
|
||||
{
|
||||
void __iomem *reg = hdmi_phy->regs + offset;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp &= ~bits;
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 bits)
|
||||
{
|
||||
void __iomem *reg = hdmi_phy->regs + offset;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp |= bits;
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 val, u32 mask)
|
||||
{
|
||||
void __iomem *reg = hdmi_phy->regs + offset;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(reg);
|
||||
tmp = (tmp & ~mask) | (val & mask);
|
||||
writel(tmp, reg);
|
||||
}
|
||||
|
||||
inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct mtk_hdmi_phy, pll_hw);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(hdmi_phy->pll);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
|
||||
|
||||
hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
|
||||
clk_disable_unprepare(hdmi_phy->pll);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops *
|
||||
mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
|
||||
{
|
||||
if (hdmi_phy && hdmi_phy->conf &&
|
||||
hdmi_phy->conf->hdmi_phy_enable_tmds &&
|
||||
hdmi_phy->conf->hdmi_phy_disable_tmds)
|
||||
return &mtk_hdmi_phy_dev_ops;
|
||||
|
||||
dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
|
||||
struct clk_init_data *clk_init)
|
||||
{
|
||||
clk_init->flags = hdmi_phy->conf->flags;
|
||||
clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mtk_hdmi_phy *hdmi_phy;
|
||||
struct resource *mem;
|
||||
struct clk *ref_clk;
|
||||
const char *ref_clk_name;
|
||||
struct clk_init_data clk_init = {
|
||||
.num_parents = 1,
|
||||
.parent_names = (const char * const *)&ref_clk_name,
|
||||
};
|
||||
|
||||
struct phy *phy;
|
||||
struct phy_provider *phy_provider;
|
||||
int ret;
|
||||
|
||||
hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
|
||||
if (!hdmi_phy)
|
||||
return -ENOMEM;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
hdmi_phy->regs = devm_ioremap_resource(dev, mem);
|
||||
if (IS_ERR(hdmi_phy->regs)) {
|
||||
ret = PTR_ERR(hdmi_phy->regs);
|
||||
dev_err(dev, "Failed to get memory resource: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ref_clk = devm_clk_get(dev, "pll_ref");
|
||||
if (IS_ERR(ref_clk)) {
|
||||
ret = PTR_ERR(ref_clk);
|
||||
dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
ref_clk_name = __clk_get_name(ref_clk);
|
||||
|
||||
ret = of_property_read_string(dev->of_node, "clock-output-names",
|
||||
&clk_init.name);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
hdmi_phy->dev = dev;
|
||||
hdmi_phy->conf =
|
||||
(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
|
||||
mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
|
||||
hdmi_phy->pll_hw.init = &clk_init;
|
||||
hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
|
||||
if (IS_ERR(hdmi_phy->pll)) {
|
||||
ret = PTR_ERR(hdmi_phy->pll);
|
||||
dev_err(dev, "Failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
|
||||
&hdmi_phy->ibias);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
|
||||
&hdmi_phy->ibias_up);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
|
||||
hdmi_phy->drv_imp_clk = 0x30;
|
||||
hdmi_phy->drv_imp_d2 = 0x30;
|
||||
hdmi_phy->drv_imp_d1 = 0x30;
|
||||
hdmi_phy->drv_imp_d0 = 0x30;
|
||||
|
||||
phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "Failed to create HDMI PHY\n");
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
phy_set_drvdata(phy, hdmi_phy);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
dev_err(dev, "Failed to register HDMI PHY\n");
|
||||
return PTR_ERR(phy_provider);
|
||||
}
|
||||
|
||||
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
|
||||
hdmi_phy->pll);
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_hdmi_phy_match[] = {
|
||||
{ .compatible = "mediatek,mt2701-hdmi-phy",
|
||||
.data = &mtk_hdmi_phy_2701_conf,
|
||||
},
|
||||
{ .compatible = "mediatek,mt8173-hdmi-phy",
|
||||
.data = &mtk_hdmi_phy_8173_conf,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
struct platform_driver mtk_hdmi_phy_driver = {
|
||||
.probe = mtk_hdmi_phy_probe,
|
||||
.driver = {
|
||||
.name = "mediatek-hdmi-phy",
|
||||
.of_match_table = mtk_hdmi_phy_match,
|
||||
},
|
||||
};
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@@ -1,57 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Chunhui Dai <chunhui.dai@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MTK_HDMI_PHY_H
|
||||
#define _MTK_HDMI_PHY_H
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct mtk_hdmi_phy;
|
||||
|
||||
struct mtk_hdmi_phy_conf {
|
||||
bool tz_disabled;
|
||||
unsigned long flags;
|
||||
const struct clk_ops *hdmi_phy_clk_ops;
|
||||
void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
|
||||
void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
|
||||
};
|
||||
|
||||
struct mtk_hdmi_phy {
|
||||
void __iomem *regs;
|
||||
struct device *dev;
|
||||
struct mtk_hdmi_phy_conf *conf;
|
||||
struct clk *pll;
|
||||
struct clk_hw pll_hw;
|
||||
unsigned long pll_rate;
|
||||
unsigned char drv_imp_clk;
|
||||
unsigned char drv_imp_d2;
|
||||
unsigned char drv_imp_d1;
|
||||
unsigned char drv_imp_d0;
|
||||
unsigned int ibias;
|
||||
unsigned int ibias_up;
|
||||
};
|
||||
|
||||
void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 bits);
|
||||
void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 bits);
|
||||
void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 val, u32 mask);
|
||||
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
|
||||
|
||||
extern struct platform_driver mtk_hdmi_phy_driver;
|
||||
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
|
||||
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
|
||||
|
||||
#endif /* _MTK_HDMI_PHY_H */
|
||||
@@ -1,249 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Chunhui Dai <chunhui.dai@mediatek.com>
|
||||
*/
|
||||
|
||||
#include "mtk_hdmi_phy.h"
|
||||
|
||||
#define HDMI_CON0 0x00
|
||||
#define RG_HDMITX_DRV_IBIAS 0
|
||||
#define RG_HDMITX_DRV_IBIAS_MASK (0x3f << 0)
|
||||
#define RG_HDMITX_EN_SER 12
|
||||
#define RG_HDMITX_EN_SER_MASK (0x0f << 12)
|
||||
#define RG_HDMITX_EN_SLDO 16
|
||||
#define RG_HDMITX_EN_SLDO_MASK (0x0f << 16)
|
||||
#define RG_HDMITX_EN_PRED 20
|
||||
#define RG_HDMITX_EN_PRED_MASK (0x0f << 20)
|
||||
#define RG_HDMITX_EN_IMP 24
|
||||
#define RG_HDMITX_EN_IMP_MASK (0x0f << 24)
|
||||
#define RG_HDMITX_EN_DRV 28
|
||||
#define RG_HDMITX_EN_DRV_MASK (0x0f << 28)
|
||||
|
||||
#define HDMI_CON1 0x04
|
||||
#define RG_HDMITX_PRED_IBIAS 18
|
||||
#define RG_HDMITX_PRED_IBIAS_MASK (0x0f << 18)
|
||||
#define RG_HDMITX_PRED_IMP (0x01 << 22)
|
||||
#define RG_HDMITX_DRV_IMP 26
|
||||
#define RG_HDMITX_DRV_IMP_MASK (0x3f << 26)
|
||||
|
||||
#define HDMI_CON2 0x08
|
||||
#define RG_HDMITX_EN_TX_CKLDO (0x01 << 0)
|
||||
#define RG_HDMITX_EN_TX_POSDIV (0x01 << 1)
|
||||
#define RG_HDMITX_TX_POSDIV 3
|
||||
#define RG_HDMITX_TX_POSDIV_MASK (0x03 << 3)
|
||||
#define RG_HDMITX_EN_MBIAS (0x01 << 6)
|
||||
#define RG_HDMITX_MBIAS_LPF_EN (0x01 << 7)
|
||||
|
||||
#define HDMI_CON4 0x10
|
||||
#define RG_HDMITX_RESERVE_MASK (0xffffffff << 0)
|
||||
|
||||
#define HDMI_CON6 0x18
|
||||
#define RG_HTPLL_BR 0
|
||||
#define RG_HTPLL_BR_MASK (0x03 << 0)
|
||||
#define RG_HTPLL_BC 2
|
||||
#define RG_HTPLL_BC_MASK (0x03 << 2)
|
||||
#define RG_HTPLL_BP 4
|
||||
#define RG_HTPLL_BP_MASK (0x0f << 4)
|
||||
#define RG_HTPLL_IR 8
|
||||
#define RG_HTPLL_IR_MASK (0x0f << 8)
|
||||
#define RG_HTPLL_IC 12
|
||||
#define RG_HTPLL_IC_MASK (0x0f << 12)
|
||||
#define RG_HTPLL_POSDIV 16
|
||||
#define RG_HTPLL_POSDIV_MASK (0x03 << 16)
|
||||
#define RG_HTPLL_PREDIV 18
|
||||
#define RG_HTPLL_PREDIV_MASK (0x03 << 18)
|
||||
#define RG_HTPLL_FBKSEL 20
|
||||
#define RG_HTPLL_FBKSEL_MASK (0x03 << 20)
|
||||
#define RG_HTPLL_RLH_EN (0x01 << 22)
|
||||
#define RG_HTPLL_FBKDIV 24
|
||||
#define RG_HTPLL_FBKDIV_MASK (0x7f << 24)
|
||||
#define RG_HTPLL_EN (0x01 << 31)
|
||||
|
||||
#define HDMI_CON7 0x1c
|
||||
#define RG_HTPLL_AUTOK_EN (0x01 << 23)
|
||||
#define RG_HTPLL_DIVEN 28
|
||||
#define RG_HTPLL_DIVEN_MASK (0x07 << 28)
|
||||
|
||||
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
|
||||
usleep_range(80, 100);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
|
||||
usleep_range(80, 100);
|
||||
}
|
||||
|
||||
static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
u32 pos_div;
|
||||
|
||||
if (rate <= 64000000)
|
||||
pos_div = 3;
|
||||
else if (rate <= 128000000)
|
||||
pos_div = 2;
|
||||
else
|
||||
pos_div = 1;
|
||||
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
|
||||
RG_HTPLL_IC_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
|
||||
RG_HTPLL_IR_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
|
||||
RG_HDMITX_TX_POSDIV_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
|
||||
RG_HTPLL_FBKSEL_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
|
||||
RG_HTPLL_FBKDIV_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
|
||||
RG_HTPLL_DIVEN_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
|
||||
RG_HTPLL_BP_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
|
||||
RG_HTPLL_BC_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
|
||||
RG_HTPLL_BR_MASK);
|
||||
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
|
||||
RG_HDMITX_PRED_IBIAS_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
|
||||
RG_HDMITX_DRV_IMP_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
|
||||
RG_HDMITX_DRV_IBIAS_MASK);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
unsigned long out_rate, val;
|
||||
|
||||
val = (readl(hdmi_phy->regs + HDMI_CON6)
|
||||
& RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
|
||||
switch (val) {
|
||||
case 0x00:
|
||||
out_rate = parent_rate;
|
||||
break;
|
||||
case 0x01:
|
||||
out_rate = parent_rate / 2;
|
||||
break;
|
||||
default:
|
||||
out_rate = parent_rate / 4;
|
||||
break;
|
||||
}
|
||||
|
||||
val = (readl(hdmi_phy->regs + HDMI_CON6)
|
||||
& RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
|
||||
out_rate *= (val + 1) * 2;
|
||||
val = (readl(hdmi_phy->regs + HDMI_CON2)
|
||||
& RG_HDMITX_TX_POSDIV_MASK);
|
||||
out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
|
||||
|
||||
if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
|
||||
out_rate /= 5;
|
||||
|
||||
return out_rate;
|
||||
}
|
||||
|
||||
static const struct clk_ops mtk_hdmi_phy_pll_ops = {
|
||||
.prepare = mtk_hdmi_pll_prepare,
|
||||
.unprepare = mtk_hdmi_pll_unprepare,
|
||||
.set_rate = mtk_hdmi_pll_set_rate,
|
||||
.round_rate = mtk_hdmi_pll_round_rate,
|
||||
.recalc_rate = mtk_hdmi_pll_recalc_rate,
|
||||
};
|
||||
|
||||
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
||||
{
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
|
||||
usleep_range(80, 100);
|
||||
}
|
||||
|
||||
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
||||
{
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
|
||||
usleep_range(80, 100);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
|
||||
usleep_range(80, 100);
|
||||
}
|
||||
|
||||
struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
|
||||
.tz_disabled = true,
|
||||
.flags = CLK_SET_RATE_GATE,
|
||||
.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
|
||||
.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
|
||||
.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
|
||||
};
|
||||
|
||||
MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
|
||||
MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@@ -1,282 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Jie Qiu <jie.qiu@mediatek.com>
|
||||
*/
|
||||
|
||||
#include "mtk_hdmi_phy.h"
|
||||
|
||||
#define HDMI_CON0 0x00
|
||||
#define RG_HDMITX_PLL_EN BIT(31)
|
||||
#define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
|
||||
#define PLL_FBKDIV_SHIFT 24
|
||||
#define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
|
||||
#define PLL_FBKSEL_SHIFT 22
|
||||
#define RG_HDMITX_PLL_PREDIV (0x3 << 20)
|
||||
#define PREDIV_SHIFT 20
|
||||
#define RG_HDMITX_PLL_POSDIV (0x3 << 18)
|
||||
#define POSDIV_SHIFT 18
|
||||
#define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
|
||||
#define RG_HDMITX_PLL_IR (0xf << 12)
|
||||
#define PLL_IR_SHIFT 12
|
||||
#define RG_HDMITX_PLL_IC (0xf << 8)
|
||||
#define PLL_IC_SHIFT 8
|
||||
#define RG_HDMITX_PLL_BP (0xf << 4)
|
||||
#define PLL_BP_SHIFT 4
|
||||
#define RG_HDMITX_PLL_BR (0x3 << 2)
|
||||
#define PLL_BR_SHIFT 2
|
||||
#define RG_HDMITX_PLL_BC (0x3 << 0)
|
||||
#define PLL_BC_SHIFT 0
|
||||
#define HDMI_CON1 0x04
|
||||
#define RG_HDMITX_PLL_DIVEN (0x7 << 29)
|
||||
#define PLL_DIVEN_SHIFT 29
|
||||
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
|
||||
#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
|
||||
#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
|
||||
#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
|
||||
#define RG_HDMITX_PLL_BAND (0x3f << 16)
|
||||
#define RG_HDMITX_PLL_REF_SEL BIT(15)
|
||||
#define RG_HDMITX_PLL_BIAS_EN BIT(14)
|
||||
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
|
||||
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
|
||||
#define RG_HDMITX_PLL_TXDIV (0x3 << 10)
|
||||
#define PLL_TXDIV_SHIFT 10
|
||||
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
|
||||
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
|
||||
#define RG_HDMITX_PLL_MONCK_EN BIT(7)
|
||||
#define RG_HDMITX_PLL_MONREF_EN BIT(6)
|
||||
#define RG_HDMITX_PLL_TST_EN BIT(5)
|
||||
#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
|
||||
#define RG_HDMITX_PLL_TST_SEL (0xf << 0)
|
||||
#define HDMI_CON2 0x08
|
||||
#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
|
||||
#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
|
||||
#define RG_HDMITX_EN_TX_CKLDO BIT(0)
|
||||
#define HDMI_CON3 0x0c
|
||||
#define RG_HDMITX_SER_EN (0xf << 28)
|
||||
#define RG_HDMITX_PRD_EN (0xf << 24)
|
||||
#define RG_HDMITX_PRD_IMP_EN (0xf << 20)
|
||||
#define RG_HDMITX_DRV_EN (0xf << 16)
|
||||
#define RG_HDMITX_DRV_IMP_EN (0xf << 12)
|
||||
#define DRV_IMP_EN_SHIFT 12
|
||||
#define RG_HDMITX_MHLCK_FORCE BIT(10)
|
||||
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
|
||||
#define RG_HDMITX_MHLCK_EN BIT(8)
|
||||
#define RG_HDMITX_SER_DIN_SEL (0xf << 4)
|
||||
#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
|
||||
#define RG_HDMITX_SER_BIST_TOG BIT(2)
|
||||
#define RG_HDMITX_SER_DIN_TOG BIT(1)
|
||||
#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
|
||||
#define HDMI_CON4 0x10
|
||||
#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
|
||||
#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
|
||||
#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
|
||||
#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
|
||||
#define PRD_IBIAS_CLK_SHIFT 24
|
||||
#define PRD_IBIAS_D2_SHIFT 16
|
||||
#define PRD_IBIAS_D1_SHIFT 8
|
||||
#define PRD_IBIAS_D0_SHIFT 0
|
||||
#define HDMI_CON5 0x14
|
||||
#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
|
||||
#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
|
||||
#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
|
||||
#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
|
||||
#define DRV_IBIAS_CLK_SHIFT 24
|
||||
#define DRV_IBIAS_D2_SHIFT 16
|
||||
#define DRV_IBIAS_D1_SHIFT 8
|
||||
#define DRV_IBIAS_D0_SHIFT 0
|
||||
#define HDMI_CON6 0x18
|
||||
#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
|
||||
#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
|
||||
#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
|
||||
#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
|
||||
#define DRV_IMP_CLK_SHIFT 24
|
||||
#define DRV_IMP_D2_SHIFT 16
|
||||
#define DRV_IMP_D1_SHIFT 8
|
||||
#define DRV_IMP_D0_SHIFT 0
|
||||
#define HDMI_CON7 0x1c
|
||||
#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
|
||||
#define RG_HDMITX_SER_DIN (0x3ff << 16)
|
||||
#define RG_HDMITX_CHLDC_TST (0xf << 12)
|
||||
#define RG_HDMITX_CHLCK_TST (0xf << 8)
|
||||
#define RG_HDMITX_RESERVE (0xff << 0)
|
||||
#define HDMI_CON8 0x20
|
||||
#define RGS_HDMITX_2T1_LEV (0xf << 16)
|
||||
#define RGS_HDMITX_2T1_EDG (0xf << 12)
|
||||
#define RGS_HDMITX_5T1_LEV (0xf << 8)
|
||||
#define RGS_HDMITX_5T1_EDG (0xf << 4)
|
||||
#define RGS_HDMITX_PLUG_TST BIT(0)
|
||||
|
||||
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
|
||||
usleep_range(100, 150);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
|
||||
usleep_range(100, 150);
|
||||
}
|
||||
|
||||
static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
hdmi_phy->pll_rate = rate;
|
||||
if (rate <= 74250000)
|
||||
*parent_rate = rate;
|
||||
else
|
||||
*parent_rate = rate / 2;
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
unsigned int pre_div;
|
||||
unsigned int div;
|
||||
unsigned int pre_ibias;
|
||||
unsigned int hdmi_ibias;
|
||||
unsigned int imp_en;
|
||||
|
||||
dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
|
||||
rate, parent_rate);
|
||||
|
||||
if (rate <= 27000000) {
|
||||
pre_div = 0;
|
||||
div = 3;
|
||||
} else if (rate <= 74250000) {
|
||||
pre_div = 1;
|
||||
div = 2;
|
||||
} else {
|
||||
pre_div = 1;
|
||||
div = 1;
|
||||
}
|
||||
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
|
||||
RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
|
||||
(div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
|
||||
RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
|
||||
(0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
|
||||
(0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
|
||||
(0x1 << PLL_BR_SHIFT),
|
||||
RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
|
||||
RG_HDMITX_PLL_BR);
|
||||
if (rate < 165000000) {
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
|
||||
RG_HDMITX_PRD_IMP_EN);
|
||||
pre_ibias = 0x3;
|
||||
imp_en = 0x0;
|
||||
hdmi_ibias = hdmi_phy->ibias;
|
||||
} else {
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
|
||||
RG_HDMITX_PRD_IMP_EN);
|
||||
pre_ibias = 0x6;
|
||||
imp_en = 0xf;
|
||||
hdmi_ibias = hdmi_phy->ibias_up;
|
||||
}
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
|
||||
(pre_ibias << PRD_IBIAS_CLK_SHIFT) |
|
||||
(pre_ibias << PRD_IBIAS_D2_SHIFT) |
|
||||
(pre_ibias << PRD_IBIAS_D1_SHIFT) |
|
||||
(pre_ibias << PRD_IBIAS_D0_SHIFT),
|
||||
RG_HDMITX_PRD_IBIAS_CLK |
|
||||
RG_HDMITX_PRD_IBIAS_D2 |
|
||||
RG_HDMITX_PRD_IBIAS_D1 |
|
||||
RG_HDMITX_PRD_IBIAS_D0);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
|
||||
(imp_en << DRV_IMP_EN_SHIFT),
|
||||
RG_HDMITX_DRV_IMP_EN);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
|
||||
(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
|
||||
(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
|
||||
(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
|
||||
(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
|
||||
RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
|
||||
RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
|
||||
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
|
||||
(hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
|
||||
(hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
|
||||
(hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
|
||||
(hdmi_ibias << DRV_IBIAS_D0_SHIFT),
|
||||
RG_HDMITX_DRV_IBIAS_CLK |
|
||||
RG_HDMITX_DRV_IBIAS_D2 |
|
||||
RG_HDMITX_DRV_IBIAS_D1 |
|
||||
RG_HDMITX_DRV_IBIAS_D0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
||||
|
||||
return hdmi_phy->pll_rate;
|
||||
}
|
||||
|
||||
static const struct clk_ops mtk_hdmi_phy_pll_ops = {
|
||||
.prepare = mtk_hdmi_pll_prepare,
|
||||
.unprepare = mtk_hdmi_pll_unprepare,
|
||||
.set_rate = mtk_hdmi_pll_set_rate,
|
||||
.round_rate = mtk_hdmi_pll_round_rate,
|
||||
.recalc_rate = mtk_hdmi_pll_recalc_rate,
|
||||
};
|
||||
|
||||
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
||||
{
|
||||
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
|
||||
RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
|
||||
RG_HDMITX_DRV_EN);
|
||||
usleep_range(100, 150);
|
||||
}
|
||||
|
||||
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
||||
{
|
||||
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
|
||||
RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
|
||||
RG_HDMITX_SER_EN);
|
||||
}
|
||||
|
||||
struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
|
||||
.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
|
||||
.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
|
||||
.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
|
||||
};
|
||||
|
||||
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
|
||||
MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Reference in New Issue
Block a user