x86/platform/intel-mid: Make vertical indentation consistent

The vertical indentation is kinda chaotic in intel-mid.h. Let's be
consistent with it.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1465992260-29897-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Andy Shevchenko
2016-06-15 15:04:20 +03:00
committed by Ingo Molnar
parent a11836fa5a
commit 06a3fcc44d

View File

@@ -108,8 +108,8 @@ static inline bool intel_mid_has_msic(void)
#else /* !CONFIG_X86_INTEL_MID */ #else /* !CONFIG_X86_INTEL_MID */
#define intel_mid_identify_cpu() (0) #define intel_mid_identify_cpu() 0
#define intel_mid_has_msic() (0) #define intel_mid_has_msic() 0
#endif /* !CONFIG_X86_INTEL_MID */ #endif /* !CONFIG_X86_INTEL_MID */
@@ -137,9 +137,12 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
/* Bus Select SoC Fuse value */ /* Bus Select SoC Fuse value */
#define BSEL_SOC_FUSE_MASK 0x7 #define BSEL_SOC_FUSE_MASK 0x7
#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ /* FSB 133MHz */
#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ #define BSEL_SOC_FUSE_001 0x1
#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ /* FSB 100MHz */
#define BSEL_SOC_FUSE_101 0x5
/* FSB 83MHz */
#define BSEL_SOC_FUSE_111 0x7
#define SFI_MTMR_MAX_NUM 8 #define SFI_MTMR_MAX_NUM 8
#define SFI_MRTC_MAX 8 #define SFI_MRTC_MAX 8
@@ -148,12 +151,12 @@ extern void intel_scu_devices_create(void);
extern void intel_scu_devices_destroy(void); extern void intel_scu_devices_destroy(void);
/* VRTC timer */ /* VRTC timer */
#define MRST_VRTC_MAP_SZ (1024) #define MRST_VRTC_MAP_SZ 1024
/*#define MRST_VRTC_PGOFFSET (0xc00) */ /* #define MRST_VRTC_PGOFFSET 0xc00 */
extern void intel_mid_rtc_init(void); extern void intel_mid_rtc_init(void);
/* the offset for the mapping of global gpio pin to irq */ /* The offset for the mapping of global gpio pin to irq */
#define INTEL_MID_IRQ_OFFSET 0x100 #define INTEL_MID_IRQ_OFFSET 0x100
#endif /* _ASM_X86_INTEL_MID_H */ #endif /* _ASM_X86_INTEL_MID_H */