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arm64: dts: imx8m: correct assigned clocks for FEC

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commit 70eacf42a93aff6589a8b91279bbfe5f73c4ca3d upstream.

CLK_ENET_TIMER assigned clocks twice, should be a typo, correct to
CLK_ENET_PHY_REF clock.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Joakim Zhang
2021-01-16 16:44:28 +08:00
committed by Greg Kroah-Hartman
parent 4cc6badff9
commit 06294e7e34
3 changed files with 12 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@@ -866,11 +866,12 @@
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>,
<&clk IMX8MM_CLK_ENET_TIMER>;
<&clk IMX8MM_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
<&clk IMX8MM_SYS_PLL2_125M>,
<&clk IMX8MM_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";

7
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@@ -753,11 +753,12 @@
assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
<&clk IMX8MN_CLK_ENET_TIMER>,
<&clk IMX8MN_CLK_ENET_REF>,
<&clk IMX8MN_CLK_ENET_TIMER>;
<&clk IMX8MN_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_SYS_PLL2_100M>,
<&clk IMX8MN_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
<&clk IMX8MN_SYS_PLL2_125M>,
<&clk IMX8MN_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";

7
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@@ -725,11 +725,12 @@
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_TIMER>,
<&clk IMX8MP_CLK_ENET_REF>,
<&clk IMX8MP_CLK_ENET_TIMER>;
<&clk IMX8MP_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
<&clk IMX8MP_SYS_PLL2_125M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";