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qed: utilize FW 8.10.10.0

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This new firmware for the qed* adpaters fixes several issues:
 - Better blocking of malicious VFs.
 - After FLR, Tx-switching [internal routing] of packets might
   be incorrect.
 - Deletion of unicast MAC filters would sometime have side-effect
   of corrupting the MAC filters configred for a device.
It also contains fixes for future qed* drivers that *hopefully* would be
sent for review in the near future.

In addition, it would allow driver some new functionality, including:
 - Allowing PF/VF driver compaitibility with old drivers [running
   pre-8.10.5.0 firmware].
 - Better debug facilities.

This would also bump the qed* driver versions to 8.10.9.20.

Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
2016-08-19 09:33:31 +03:00
committed by David S. Miller
parent 75d67207bf
commit 05fafbfb3d
14 changed files with 1372 additions and 722 deletions
Download Patch File Download Diff File Expand all files Collapse all files

359
include/linux/qed/common_hsi.h
View File

@@ -5,28 +5,83 @@
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef _COMMON_HSI_H
#define _COMMON_HSI_H
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
#include <linux/slab.h>
/* dma_addr_t manip */
#define DMA_LO(x) ((u32)(((dma_addr_t)(x)) & 0xffffffff))
#define DMA_HI(x) ((u32)(((dma_addr_t)(x)) >> 32))
#define DMA_LO_LE(x) cpu_to_le32(DMA_LO(x))
#define DMA_HI_LE(x) cpu_to_le32(DMA_HI(x))
/* It's assumed that whoever includes this has previously included an hsi
* file defining the regpair.
*/
#define DMA_REGPAIR_LE(x, val) (x).hi = DMA_HI_LE((val)); \
(x).lo = DMA_LO_LE((val))
#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
#define HILO_DMA(hi, lo) HILO_GEN(hi, lo, dma_addr_t)
#define HILO_64(hi, lo) HILO_GEN(hi, lo, u64)
#define HILO_DMA_REGPAIR(regpair) (HILO_DMA(regpair.hi, regpair.lo))
#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
#ifndef __COMMON_HSI__
#define __COMMON_HSI__
#define CORE_SPQE_PAGE_SIZE_BYTES 4096
#define X_FINAL_CLEANUP_AGG_INT 1
#define EVENT_RING_PAGE_SIZE_BYTES 4096
#define NUM_OF_GLOBAL_QUEUES 128
#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
#define ISCSI_CDU_TASK_SEG_TYPE 0
#define RDMA_CDU_TASK_SEG_TYPE 1
#define FW_ASSERT_GENERAL_ATTN_IDX 32
#define MAX_PINNED_CCFC 32
/* Queue Zone sizes in bytes */
#define TSTORM_QZONE_SIZE 8
#define MSTORM_QZONE_SIZE 0
#define MSTORM_QZONE_SIZE 16
#define USTORM_QZONE_SIZE 8
#define XSTORM_QZONE_SIZE 8
#define YSTORM_QZONE_SIZE 0
#define PSTORM_QZONE_SIZE 0
#define ETH_MAX_NUM_RX_QUEUES_PER_VF 16
#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
/********************************/
/* CORE (LIGHT L2) FW CONSTANTS */
/********************************/
#define CORE_LL2_MAX_RAMROD_PER_CON 8
#define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096
#define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096
#define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096
#define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1
#define CORE_LL2_TX_MAX_BDS_PER_PACKET 12
#define CORE_SPQE_PAGE_SIZE_BYTES 4096
#define MAX_NUM_LL2_RX_QUEUES 32
#define MAX_NUM_LL2_TX_STATS_COUNTERS 32
#define FW_MAJOR_VERSION 8
#define FW_MINOR_VERSION 10
#define FW_REVISION_VERSION 5
#define FW_REVISION_VERSION 10
#define FW_ENGINEERING_VERSION 0
/***********************/
@@ -83,6 +138,17 @@
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
/* Clock values */
#define MASTER_CLK_FREQ_E4 (375e6)
#define STORM_CLK_FREQ_E4 (1000e6)
#define CLK25M_CLK_FREQ_E4 (25e6)
/* Global PXP windows (GTT) */
#define NUM_OF_GTT 19
#define GTT_DWORD_SIZE_BITS 10
#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
/*****************/
/* CDU CONSTANTS */
/*****************/
@@ -90,6 +156,8 @@
#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
/*****************/
/* DQ CONSTANTS */
/*****************/
@@ -115,6 +183,11 @@
#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
/* UCM agg val selection (HW) */
#define DQ_UCM_AGG_VAL_SEL_WORD0 0
@@ -159,13 +232,16 @@
#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
/* XCM agg counter flag selection */
#define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
/* UCM agg counter flag selection (HW) */
#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
@@ -178,9 +254,45 @@
#define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
/* UCM agg counter flag selection (FW) */
#define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
#define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
/* TCM agg counter flag selection (HW) */
#define DQ_TCM_AGG_FLG_SHIFT_CF0 0
#define DQ_TCM_AGG_FLG_SHIFT_CF1 1
#define DQ_TCM_AGG_FLG_SHIFT_CF2 2
#define DQ_TCM_AGG_FLG_SHIFT_CF3 3
#define DQ_TCM_AGG_FLG_SHIFT_CF4 4
#define DQ_TCM_AGG_FLG_SHIFT_CF5 5
#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
/* TCM agg counter flag selection (FW) */
#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
/* PWM address mapping */
#define DQ_PWM_OFFSET_DPM_BASE 0x0
#define DQ_PWM_OFFSET_DPM_END 0x27
#define DQ_PWM_OFFSET_XCM16_BASE 0x40
#define DQ_PWM_OFFSET_XCM32_BASE 0x44
#define DQ_PWM_OFFSET_UCM16_BASE 0x48
#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
#define DQ_PWM_OFFSET_UCM16_4 0x50
#define DQ_PWM_OFFSET_TCM16_BASE 0x58
#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4)
#define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2)
#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
#define DQ_REGION_SHIFT (12)
/* DPM */
@@ -214,15 +326,17 @@
*/
#define CM_TX_PQ_BASE 0x200
/* number of global Vport/QCN rate limiters */
#define MAX_QM_GLOBAL_RLS 256
/* QM registers data */
#define QM_LINE_CRD_REG_WIDTH 16
#define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
#define QM_BYTE_CRD_REG_WIDTH 24
#define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
#define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1))
#define QM_WFQ_CRD_REG_WIDTH 32
#define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
#define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1))
#define QM_RL_CRD_REG_WIDTH 32
#define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1))
#define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1))
/*****************/
/* CAU CONSTANTS */
@@ -287,6 +401,17 @@
/* PXP CONSTANTS */
/*****************/
/* Bars for Blocks */
#define PXP_BAR_GRC 0
#define PXP_BAR_TSDM 0
#define PXP_BAR_USDM 0
#define PXP_BAR_XSDM 0
#define PXP_BAR_MSDM 0
#define PXP_BAR_YSDM 0
#define PXP_BAR_PSDM 0
#define PXP_BAR_IGU 0
#define PXP_BAR_DQ 1
/* PTT and GTT */
#define PXP_NUM_PF_WINDOWS 12
#define PXP_PER_PF_ENTRY_SIZE 8
@@ -334,6 +459,52 @@
(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
/* PF BAR */
#define PXP_BAR0_START_GRC 0x0000
#define PXP_BAR0_GRC_LENGTH 0x1C00000
#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
PXP_BAR0_GRC_LENGTH - 1)
#define PXP_BAR0_START_IGU 0x1C00000
#define PXP_BAR0_IGU_LENGTH 0x10000
#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
PXP_BAR0_IGU_LENGTH - 1)
#define PXP_BAR0_START_TSDM 0x1C80000
#define PXP_BAR0_SDM_LENGTH 0x40000
#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_MSDM 0x1D00000
#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_USDM 0x1D80000
#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_XSDM 0x1E00000
#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_YSDM 0x1E80000
#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_PSDM 0x1F00000
#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
/* VF BAR */
#define PXP_VF_BAR0 0
#define PXP_VF_BAR0_START_GRC 0x3E00
#define PXP_VF_BAR0_GRC_LENGTH 0x200
#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
PXP_VF_BAR0_GRC_LENGTH - 1)
#define PXP_VF_BAR0_START_IGU 0
#define PXP_VF_BAR0_IGU_LENGTH 0x3000
@@ -399,6 +570,20 @@
#define PXP_NUM_ILT_RECORDS_BB 7600
#define PXP_NUM_ILT_RECORDS_K2 11000
#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
#define PXP_QUEUES_ZONE_MAX_NUM 320
/*****************/
/* PRM CONSTANTS */
/*****************/
#define PRM_DMA_PAD_BYTES_NUM 2
/******************/
/* SDMs CONSTANTS */
/******************/
#define SDM_OP_GEN_TRIG_NONE 0
#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
#define SDM_OP_GEN_TRIG_AGG_INT 2
#define SDM_OP_GEN_TRIG_LOADER 4
#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
#define SDM_OP_GEN_TRIG_RELEASE_THREAD 7
#define SDM_COMP_TYPE_NONE 0
#define SDM_COMP_TYPE_WAKE_THREAD 1
@@ -424,6 +609,8 @@
/* PRS CONSTANTS */
/*****************/
#define PRS_GFT_CAM_LINES_NO_MATCH 31
/* Async data KCQ CQE */
struct async_data {
__le32 cid;
@@ -440,20 +627,6 @@ struct coalescing_timeset {
#define COALESCING_TIMESET_VALID_SHIFT 7
};
struct common_prs_pf_msg_info {
__le32 value;
#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_SHIFT 0
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_SHIFT 1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_SHIFT 2
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_SHIFT 3
#define COMMON_PRS_PF_MSG_INFO_RESERVED_MASK 0xFFFFFFF
#define COMMON_PRS_PF_MSG_INFO_RESERVED_SHIFT 4
};
struct common_queue_zone {
__le16 ring_drv_data_consumer;
__le16 reserved;
@@ -473,6 +646,19 @@ struct vf_pf_channel_eqe_data {
struct regpair msg_addr;
};
struct iscsi_eqe_data {
__le32 cid;
__le16 conn_id;
u8 error_code;
u8 error_pdu_opcode_reserved;
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
#define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
};
struct malicious_vf_eqe_data {
u8 vf_id;
u8 err_id;
@@ -488,6 +674,7 @@ struct initial_cleanup_eqe_data {
union event_ring_data {
u8 bytes[8];
struct vf_pf_channel_eqe_data vf_pf_channel;
struct iscsi_eqe_data iscsi_info;
struct malicious_vf_eqe_data malicious_vf;
struct initial_cleanup_eqe_data vf_init_cleanup;
};
@@ -616,6 +803,52 @@ enum db_dest {
MAX_DB_DEST
};
/* Enum of doorbell DPM types */
enum db_dpm_type {
DPM_LEGACY,
DPM_ROCE,
DPM_L2_INLINE,
DPM_L2_BD,
MAX_DB_DPM_TYPE
};
/* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */
struct db_l2_dpm_data {
__le16 icid;
__le16 bd_prod;
__le32 params;
#define DB_L2_DPM_DATA_SIZE_MASK 0x3F
#define DB_L2_DPM_DATA_SIZE_SHIFT 0
#define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6
#define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF
#define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8
#define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16
#define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
#define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
#define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
#define DB_L2_DPM_DATA_RESERVED1_MASK 0x1
#define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
};
/* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
struct db_l2_dpm_sge {
struct regpair addr;
__le16 nbytes;
__le16 bitfields;
#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
__le32 reserved2;
};
/* Structure for doorbell address, in legacy mode */
struct db_legacy_addr {
__le32 addr;
@@ -627,6 +860,49 @@ struct db_legacy_addr {
#define DB_LEGACY_ADDR_ICID_SHIFT 5
};
/* Structure for doorbell address, in PWM mode */
struct db_pwm_addr {
__le32 addr;
#define DB_PWM_ADDR_RESERVED0_MASK 0x7
#define DB_PWM_ADDR_RESERVED0_SHIFT 0
#define DB_PWM_ADDR_OFFSET_MASK 0x7F
#define DB_PWM_ADDR_OFFSET_SHIFT 3
#define DB_PWM_ADDR_WID_MASK 0x3
#define DB_PWM_ADDR_WID_SHIFT 10
#define DB_PWM_ADDR_DPI_MASK 0xFFFF
#define DB_PWM_ADDR_DPI_SHIFT 12
#define DB_PWM_ADDR_RESERVED1_MASK 0xF
#define DB_PWM_ADDR_RESERVED1_SHIFT 28
};
/* Parameters to RoCE firmware, passed in EDPM doorbell */
struct db_roce_dpm_params {
__le32 params;
#define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F
#define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6
#define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF
#define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16
#define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1
#define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
#define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1
#define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29
#define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3
#define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30
};
/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */
struct db_roce_dpm_data {
__le16 icid;
__le16 prod_val;
struct db_roce_dpm_params params;
};
/* Igu interrupt command */
enum igu_int_cmd {
IGU_INT_ENABLE = 0,
@@ -764,6 +1040,19 @@ struct pxp_ptt_entry {
struct pxp_pretend_cmd pretend;
};
/* VF Zone A Permission Register. */
struct pxp_vf_zone_a_permission {
__le32 control;
#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
};
/* RSS hash type */
struct rdif_task_context {
__le32 initial_ref_tag;
@@ -831,6 +1120,7 @@ struct rdif_task_context {
__le32 reserved2;
};
/* RSS hash type */
enum rss_hash_type {
RSS_HASH_TYPE_DEFAULT = 0,
RSS_HASH_TYPE_IPV4 = 1,
@@ -942,7 +1232,7 @@ struct tdif_task_context {
};
struct timers_context {
__le32 logical_client0;
__le32 logical_client_0;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
@@ -951,7 +1241,7 @@ struct timers_context {
#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
#define TIMERS_CONTEXT_RESERVED0_MASK 0x3
#define TIMERS_CONTEXT_RESERVED0_SHIFT 30
__le32 logical_client1;
__le32 logical_client_1;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
@@ -960,7 +1250,7 @@ struct timers_context {
#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
__le32 logical_client2;
__le32 logical_client_2;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
@@ -978,3 +1268,4 @@ struct timers_context {
#define TIMERS_CONTEXT_RESERVED3_SHIFT 29
};
#endif /* __COMMON_HSI__ */
#endif