sparc64: T5 PMU
The T5 (niagara5) has different PCR related HV fast trap values and a new HV API Group. This patch utilizes these and shares when possible with niagara4. We use the same sparc_pmu niagara4_pmu. Should there be new effort to obtain the MCU perf statistics then this would have to be changed. Cc: sparclinux@vger.kernel.org Signed-off-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller

parent
7c21d533ab
commit
05aa1651e8
@@ -821,3 +821,19 @@ ENTRY(sun4v_vt_set_perfreg)
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retl
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nop
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ENDPROC(sun4v_vt_set_perfreg)
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ENTRY(sun4v_t5_get_perfreg)
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mov %o1, %o4
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mov HV_FAST_T5_GET_PERFREG, %o5
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ta HV_FAST_TRAP
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stx %o1, [%o4]
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retl
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nop
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ENDPROC(sun4v_t5_get_perfreg)
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ENTRY(sun4v_t5_set_perfreg)
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mov HV_FAST_T5_SET_PERFREG, %o5
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ta HV_FAST_TRAP
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retl
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nop
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ENDPROC(sun4v_t5_set_perfreg)
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