Merge tag 'arc-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta - Jump Label support for ARC - kmemleak enabled - arc mm backend TLB Miss / flush optimizations - nSIM platform switching to dwuart (vs. arcuart) and ensuing defconfig updates and cleanups - axs platform pll / video-mode updates * tag 'arc-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: add kmemleak support ARC: [plat-axs10x]: remove hardcoded video mode from bootargs ARC: [plat-axs10x]: use pgu pll instead of fixed clock ARC: ARCv2: jump label: implement jump label patching ARC: mm: tlb flush optim: elide redundant uTLB invalidates for MMUv3 ARC: mm: tlb flush optim: elide repeated uTLB invalidate in loop ARC: mm: tlb flush optim: Make TLBWriteNI fallback to TLBWrite if not available ARC: mm: TLB Miss optim: avoid re-reading ECR ARCv2: mm: TLB Miss optim: Use double world load/stores LDD/STD ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg ARC: nSIM_700: remove unused network options ARC: nSIM_700: switch to DW UART usage ARC: merge HAPS-HS with nSIM-HS configs ARC: HAPS: cleanup defconfigs from unused ETH drivers ARC: HAPS: add HIGHMEM memory zone to DTS ARC: HAPS: use same UART configuration everywhere ARC: HAPS: cleanup defconfigs from unused IO-related options ARC: regenerate nSIM and HAPS defconfigs
This commit is contained in:
Linus Torvalds
@@ -28,6 +28,12 @@
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clock-frequency = <750000000>;
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};
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input_clk: input-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <33333333>;
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};
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core_intc: arc700-intc@cpu {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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@@ -14,6 +14,6 @@
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compatible = "snps,axs101", "snps,arc-sdp";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60 print-fatal-signals=1";
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bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 print-fatal-signals=1";
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};
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};
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@@ -17,6 +17,6 @@
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compatible = "snps,axs103", "snps,arc-sdp";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0 video=1280x720@60";
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bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0";
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};
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};
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@@ -61,12 +61,13 @@
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clock-frequency = <25000000>;
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#clock-cells = <0>;
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};
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};
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pguclk: pguclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <74250000>;
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};
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pguclk: pguclk@10080 {
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compatible = "snps,axs10x-pgu-pll-clock";
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reg = <0x10080 0x10>, <0x110 0x10>;
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#clock-cells = <0>;
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clocks = <&input_clk>;
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};
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gmac: ethernet@18000 {
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@@ -9,13 +9,15 @@
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/ {
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model = "snps,zebu_hs";
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compatible = "snps,zebu_hs";
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#address-cells = <1>;
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#size-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&core_intc>;
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memory {
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512 */
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/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
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reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
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0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
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};
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chosen {
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@@ -31,8 +33,9 @@
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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/* only perip space at end of low mem accessible
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bus addr, parent bus addr, size */
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ranges = <0x80000000 0x0 0x80000000 0x80000000>;
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core_clk: core_clk {
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#clock-cells = <0>;
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@@ -47,7 +50,7 @@
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};
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uart0: serial@f0000000 {
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compatible = "ns8250";
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compatible = "ns16550a";
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reg = <0xf0000000 0x2000>;
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interrupts = <24>;
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clock-frequency = <50000000>;
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@@ -54,7 +54,6 @@
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};
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uart0: serial@f0000000 {
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/* compatible = "ns8250"; Doesn't use FIFOs */
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compatible = "ns16550a";
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reg = <0xf0000000 0x2000>;
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interrupt-parent = <&idu_intc>;
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@@ -14,11 +14,11 @@
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interrupt-parent = <&core_intc>;
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chosen {
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bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
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bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signals=1";
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};
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aliases {
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serial0 = &arcuart0;
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serial0 = &uart0;
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};
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fpga {
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@@ -41,29 +41,15 @@
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupts = <5>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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};
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ethernet@c0fc2000 {
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compatible = "snps,arc-emac";
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reg = <0xc0fc2000 0x3c>;
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interrupts = <6>;
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mac-address = [ 00 11 22 33 44 55 ];
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clock-frequency = <80000000>;
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max-speed = <100>;
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phy = <&phy0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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uart0: serial@f0000000 {
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compatible = "ns16550a";
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reg = <0xf0000000 0x2000>;
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interrupts = <24>;
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clock-frequency = <50000000>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test = <1>;
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};
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arcpct0: pct {
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@@ -1,67 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*/
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/dts-v1/;
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/include/ "skeleton_hs.dtsi"
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/ {
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model = "snps,nsim_hs";
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compatible = "snps,nsim_hs";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&core_intc>;
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memory {
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device_type = "memory";
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/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
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reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
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0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
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};
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chosen {
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bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
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};
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aliases {
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serial0 = &arcuart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* only perip space at end of low mem accessible
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bus addr, parent bus addr, size */
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ranges = <0x80000000 0x0 0x80000000 0x80000000>;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <80000000>;
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};
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupts = <24>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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};
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arcpct0: pct {
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compatible = "snps,archs-pct";
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#interrupt-cells = <1>;
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interrupts = <20>;
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};
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};
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};
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@@ -1,65 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*/
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/dts-v1/;
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/include/ "skeleton_hs_idu.dtsi"
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/ {
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model = "snps,nsim_hs-smp";
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compatible = "snps,nsim_hs";
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interrupt-parent = <&core_intc>;
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chosen {
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bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
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};
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aliases {
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serial0 = &arcuart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <80000000>;
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};
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupt-parent = <&idu_intc>;
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interrupts = <0>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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};
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arcpct0: pct {
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compatible = "snps,archs-pct";
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#interrupt-cells = <1>;
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interrupts = <20>;
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};
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};
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};
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Block a user