Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (45 commits) crypto: caam - add support for sha512 variants of existing AEAD algorithms crypto: caam - remove unused authkeylen from caam_ctx crypto: caam - fix decryption shared vs. non-shared key setting crypto: caam - platform_bus_type migration crypto: aesni-intel - fix aesni build on i386 crypto: aesni-intel - Merge with fpu.ko crypto: mv_cesa - make count_sgs() null-pointer proof crypto: mv_cesa - copy remaining bytes to SRAM only when needed crypto: mv_cesa - move digest state initialisation to a better place crypto: mv_cesa - fill inner/outer IV fields only in HMAC case crypto: mv_cesa - refactor copy_src_to_buf() crypto: mv_cesa - no need to save digest state after the last chunk crypto: mv_cesa - print a warning when registration of AES algos fail crypto: mv_cesa - drop this call to mv_hash_final from mv_hash_finup crypto: mv_cesa - the descriptor pointer register needs to be set just once crypto: mv_cesa - use ablkcipher_request_cast instead of the manual container_of crypto: caam - fix printk recursion for long error texts crypto: caam - remove unused keylen from session context hwrng: amd - enable AMD hw rnd driver for Maple PPC boards hwrng: amd - manage resource allocation ...
This commit is contained in:
Linus Torvalds
397
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
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397
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
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=====================================================================
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SEC 4 Device Tree Binding
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Copyright (C) 2008-2011 Freescale Semiconductor Inc.
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CONTENTS
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-Overview
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-SEC 4 Node
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-Job Ring Node
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-Run Time Integrity Check (RTIC) Node
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-Run Time Integrity Check (RTIC) Memory Node
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-Secure Non-Volatile Storage (SNVS) Node
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-Full Example
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NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
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Accelerator and Assurance Module (CAAM).
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=====================================================================
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Overview
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DESCRIPTION
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SEC 4 h/w can process requests from 2 types of sources.
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1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
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2. Job Rings (HW interface between cores & SEC 4 registers).
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High Speed Data Path Configuration:
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HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
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such as the P4080. The number of simultaneous dequeues the QI can make is
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equal to the number of Descriptor Controller (DECO) engines in a particular
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SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
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dequeue from 5 subportals simultaneously.
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Job Ring Data Path Configuration:
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Each JR is located on a separate 4k page, they may (or may not) be made visible
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in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
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up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
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=====================================================================
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SEC 4 Node
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Description
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Node defines the base address of the SEC 4 block.
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This block specifies the address range of all global
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configuration registers for the SEC 4 block. It
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also receives interrupts from the Run Time Integrity Check
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(RTIC) function within the SEC 4 block.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0"
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing physical addresses in child nodes.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing the size of physical addresses in
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child nodes.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical
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address and length of the SEC4 configuration registers.
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registers
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- ranges
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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range of the SEC 4.0 register space (-SNVS not included). A
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triplet that includes the child address, parent address, &
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length.
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- interrupts
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Usage: required
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Value type: <prop_encoded-array>
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Definition: Specifies the interrupts generated by this
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device. The value of the interrupts property
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consists of one interrupt specifier. The format
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of the specifier is defined by the binding document
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describing the node's interrupt parent.
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- interrupt-parent
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Usage: (required if interrupt property is defined)
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Value type: <phandle>
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Definition: A single <phandle> value that points
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to the interrupt parent to which the child domain
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is being mapped.
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Note: All other standard properties (see the ePAPR) are allowed
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but are optional.
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EXAMPLE
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crypto@300000 {
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compatible = "fsl,sec-v4.0";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x300000 0x10000>;
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ranges = <0 0x300000 0x10000>;
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interrupt-parent = <&mpic>;
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interrupts = <92 2>;
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};
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=====================================================================
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Job Ring (JR) Node
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Child of the crypto node defines data processing interface to SEC 4
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across the peripheral bus for purposes of processing
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cryptographic descriptors. The specified address
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range can be made visible to one (or more) cores.
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The interrupt defined for this node is controlled within
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the address range of this node.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0-job-ring"
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Specifies a two JR parameters: an offset from
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the parent physical address and the length the JR registers.
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- fsl,liodn
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Usage: optional-but-recommended
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Value type: <prop-encoded-array>
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Definition:
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Specifies the LIODN to be used in conjunction with
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the ppid-to-liodn table that specifies the PPID to LIODN mapping.
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Needed if the PAMU is used. Value is a 12 bit value
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where value is a LIODN ID for this JR. This property is
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normally set by boot firmware.
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- interrupts
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Usage: required
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Value type: <prop_encoded-array>
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Definition: Specifies the interrupts generated by this
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device. The value of the interrupts property
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consists of one interrupt specifier. The format
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of the specifier is defined by the binding document
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describing the node's interrupt parent.
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- interrupt-parent
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Usage: (required if interrupt property is defined)
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Value type: <phandle>
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Definition: A single <phandle> value that points
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to the interrupt parent to which the child domain
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is being mapped.
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EXAMPLE
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jr@1000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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fsl,liodn = <0x081>;
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interrupt-parent = <&mpic>;
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interrupts = <88 2>;
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};
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=====================================================================
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Run Time Integrity Check (RTIC) Node
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Child node of the crypto node. Defines a register space that
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contains up to 5 sets of addresses and their lengths (sizes) that
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will be checked at run time. After an initial hash result is
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calculated, these addresses are checked by HW to monitor any
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change. If any memory is modified, a Security Violation is
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triggered (see SNVS definition).
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0-rtic".
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing physical addresses in child nodes. Must
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have a value of 1.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing the size of physical addresses in
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child nodes. Must have a value of 1.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies a two parameters:
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an offset from the parent physical address and the length
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the SEC4 registers.
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- ranges
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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range of the SEC 4 register space (-SNVS not included). A
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triplet that includes the child address, parent address, &
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length.
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EXAMPLE
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rtic@6000 {
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compatible = "fsl,sec-v4.0-rtic";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x6000 0x100>;
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ranges = <0x0 0x6100 0xe00>;
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};
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=====================================================================
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Run Time Integrity Check (RTIC) Memory Node
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A child node that defines individual RTIC memory regions that are used to
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perform run-time integrity check of memory areas that should not modified.
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The node defines a register that contains the memory address &
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length (combined) and a second register that contains the hash result
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in big endian format.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0-rtic-memory".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies two parameters:
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an offset from the parent physical address and the length:
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1. The location of the RTIC memory address & length registers.
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2. The location RTIC hash result.
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- fsl,rtic-region
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Usage: optional-but-recommended
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Value type: <prop-encoded-array>
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Definition:
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Specifies the HW address (36 bit address) for this region
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followed by the length of the HW partition to be checked;
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the address is represented as a 64 bit quantity followed
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by a 32 bit length.
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- fsl,liodn
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Usage: optional-but-recommended
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Value type: <prop-encoded-array>
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Definition:
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Specifies the LIODN to be used in conjunction with
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the ppid-to-liodn table that specifies the PPID to LIODN
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mapping. Needed if the PAMU is used. Value is a 12 bit value
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where value is a LIODN ID for this RTIC memory region. This
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property is normally set by boot firmware.
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EXAMPLE
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rtic-a@0 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x00 0x20 0x100 0x80>;
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fsl,liodn = <0x03c>;
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fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
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};
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=====================================================================
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Secure Non-Volatile Storage (SNVS) Node
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Node defines address range and the associated
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interrupt for the SNVS function. This function
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monitors security state information & reports
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security violations.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0-mon".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical
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address and length of the SEC4 configuration
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registers.
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- interrupts
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Usage: required
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Value type: <prop_encoded-array>
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Definition: Specifies the interrupts generated by this
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device. The value of the interrupts property
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consists of one interrupt specifier. The format
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of the specifier is defined by the binding document
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describing the node's interrupt parent.
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- interrupt-parent
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Usage: (required if interrupt property is defined)
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Value type: <phandle>
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Definition: A single <phandle> value that points
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to the interrupt parent to which the child domain
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is being mapped.
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EXAMPLE
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sec_mon@314000 {
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compatible = "fsl,sec-v4.0-mon";
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reg = <0x314000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <93 2>;
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};
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=====================================================================
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FULL EXAMPLE
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crypto: crypto@300000 {
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compatible = "fsl,sec-v4.0";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x300000 0x10000>;
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ranges = <0 0x300000 0x10000>;
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interrupt-parent = <&mpic>;
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interrupts = <92 2>;
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sec_jr0: jr@1000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <88 2>;
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};
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sec_jr1: jr@2000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <89 2>;
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};
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sec_jr2: jr@3000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x3000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <90 2>;
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};
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sec_jr3: jr@4000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x4000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <91 2>;
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};
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rtic@6000 {
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compatible = "fsl,sec-v4.0-rtic";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x6000 0x100>;
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ranges = <0x0 0x6100 0xe00>;
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rtic_a: rtic-a@0 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x00 0x20 0x100 0x80>;
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};
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rtic_b: rtic-b@20 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x20 0x20 0x200 0x80>;
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};
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rtic_c: rtic-c@40 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x40 0x20 0x300 0x80>;
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};
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rtic_d: rtic-d@60 {
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compatible = "fsl,sec-v4.0-rtic-memory";
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reg = <0x60 0x20 0x500 0x80>;
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};
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};
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};
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sec_mon: sec_mon@314000 {
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compatible = "fsl,sec-v4.0-mon";
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reg = <0x314000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <93 2>;
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};
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=====================================================================
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