xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

mtd: rawnand: arasan: Fix clock rate in NV-DDR

Browse Source 
[ Upstream commit e16eceea863b417fd328588b1be1a79de0bc937f ]

According to the Arasan NAND controller spec, the flash clock rate for SDR
must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
which would result in incorrect behavior for NV-DDR modes 0-4.

The appropriate clock rate can be calculated from the NV-DDR timing
parameters as 1/tCK, or for rates measured in picoseconds,
10^12 / nand_nvddr_timings->tCK_min.

Fixes: 197b88fecc ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@vger.kernel.org # 5.8+
Signed-off-by: Olga Kitaina <okitain@gmail.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Olga Kitaina
2022-06-28 21:18:24 +05:30
committed by Greg Kroah-Hartman
parent dc0e4a10b4
commit 04c9d23ac3
1 changed files with 7 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/mtd/nand/raw/arasan-nand-controller.c
View File

@@ -907,7 +907,13 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,
anand->timings = DIFACE_NVDDR | anand->timings = DIFACE_NVDDR |
DIFACE_DDR_MODE(conf->timings.mode); DIFACE_DDR_MODE(conf->timings.mode);
if (nand_interface_is_sdr(conf)) {
anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
} else {
/* ONFI timings are defined in picoseconds */
anand->clk = div_u64((u64)NSEC_PER_SEC * 1000,
conf->timings.nvddr.tCK_min);
}
/* /*
* Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work