ARM: 8757/1: NOMMU: Support PMSAv8 MPU
ARMv8R/M architecture defines new memory protection scheme - PMSAv8 which is not compatible with PMSAv7. Key differences to PMSAv7 are: - Region geometry is defined by base and limit addresses - Addresses need to be either 32 or 64 byte aligned - No region priority due to overlapping regions are not allowed - It is unified, i.e. no distinction between data/instruction regions - Memory attributes are controlled via MAIR This patch implements support for PMSAv8 MPU defined by ARMv8R/M architecture. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Vladimir Murzin
committed by
Russell King
Russell King
parent
3c24121039
commit
046835b4aa
@@ -10,7 +10,7 @@ obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \
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ifneq ($(CONFIG_MMU),y)
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obj-y += nommu.o
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obj-$(CONFIG_ARM_MPU) += pmsa-v7.o
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obj-$(CONFIG_ARM_MPU) += pmsa-v7.o pmsa-v8.o
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endif
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obj-$(CONFIG_ARM_PTDUMP_CORE) += dump.o
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@@ -107,6 +107,9 @@ static void __init adjust_lowmem_bounds_mpu(void)
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case MMFR0_PMSAv7:
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pmsav7_adjust_lowmem_bounds();
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break;
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case MMFR0_PMSAv8:
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pmsav8_adjust_lowmem_bounds();
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break;
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default:
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break;
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}
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@@ -120,6 +123,9 @@ static void __init mpu_setup(void)
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case MMFR0_PMSAv7:
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pmsav7_setup();
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break;
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case MMFR0_PMSAv8:
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pmsav8_setup();
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break;
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default:
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break;
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}
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307
arch/arm/mm/pmsa-v8.c
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307
arch/arm/mm/pmsa-v8.c
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@@ -0,0 +1,307 @@
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/*
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* Based on linux/arch/arm/pmsa-v7.c
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*
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* ARM PMSAv8 supporting functions.
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*/
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#include <linux/memblock.h>
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#include <linux/range.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/mpu.h>
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#include <asm/memory.h>
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#include <asm/sections.h>
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#include "mm.h"
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#ifndef CONFIG_CPU_V7M
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#define PRSEL __ACCESS_CP15(c6, 0, c2, 1)
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#define PRBAR __ACCESS_CP15(c6, 0, c3, 0)
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#define PRLAR __ACCESS_CP15(c6, 0, c3, 1)
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static inline u32 prlar_read(void)
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{
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return read_sysreg(PRLAR);
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}
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static inline u32 prbar_read(void)
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{
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return read_sysreg(PRBAR);
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}
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static inline void prsel_write(u32 v)
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{
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write_sysreg(v, PRSEL);
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}
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static inline void prbar_write(u32 v)
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{
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write_sysreg(v, PRBAR);
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}
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static inline void prlar_write(u32 v)
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{
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write_sysreg(v, PRLAR);
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}
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#else
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static inline u32 prlar_read(void)
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{
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return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR);
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}
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static inline u32 prbar_read(void)
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{
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return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR);
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}
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static inline void prsel_write(u32 v)
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{
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writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
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}
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static inline void prbar_write(u32 v)
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{
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writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);
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}
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static inline void prlar_write(u32 v)
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{
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writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);
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}
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#endif
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static struct range __initdata io[MPU_MAX_REGIONS];
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static struct range __initdata mem[MPU_MAX_REGIONS];
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static unsigned int __initdata mpu_max_regions;
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static __init bool is_region_fixed(int number)
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{
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switch (number) {
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case PMSAv8_XIP_REGION:
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case PMSAv8_KERNEL_REGION:
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return true;
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default:
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return false;
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}
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}
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void __init pmsav8_adjust_lowmem_bounds(void)
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{
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phys_addr_t mem_end;
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struct memblock_region *reg;
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bool first = true;
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for_each_memblock(memory, reg) {
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if (first) {
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phys_addr_t phys_offset = PHYS_OFFSET;
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/*
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* Initially only use memory continuous from
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* PHYS_OFFSET */
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if (reg->base != phys_offset)
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panic("First memory bank must be contiguous from PHYS_OFFSET");
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mem_end = reg->base + reg->size;
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first = false;
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} else {
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/*
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* memblock auto merges contiguous blocks, remove
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* all blocks afterwards in one go (we can't remove
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* blocks separately while iterating)
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*/
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pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
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&mem_end, ®->base);
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memblock_remove(reg->base, 0 - reg->base);
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break;
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}
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}
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}
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static int __init __mpu_max_regions(void)
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{
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static int max_regions;
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u32 mpuir;
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if (max_regions)
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return max_regions;
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mpuir = read_cpuid_mputype();
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max_regions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
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return max_regions;
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}
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static int __init __pmsav8_setup_region(unsigned int number, u32 bar, u32 lar)
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{
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if (number > mpu_max_regions
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|| number >= MPU_MAX_REGIONS)
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return -ENOENT;
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dsb();
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prsel_write(number);
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isb();
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prbar_write(bar);
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prlar_write(lar);
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mpu_rgn_info.rgns[number].prbar = bar;
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mpu_rgn_info.rgns[number].prlar = lar;
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mpu_rgn_info.used++;
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return 0;
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}
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static int __init pmsav8_setup_ram(unsigned int number, phys_addr_t start,phys_addr_t end)
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{
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u32 bar, lar;
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if (is_region_fixed(number))
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return -EINVAL;
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bar = start;
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lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);;
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bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED;
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lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN;
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return __pmsav8_setup_region(number, bar, lar);
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}
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static int __init pmsav8_setup_io(unsigned int number, phys_addr_t start,phys_addr_t end)
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{
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u32 bar, lar;
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if (is_region_fixed(number))
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return -EINVAL;
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bar = start;
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lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);;
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bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN;
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lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN;
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return __pmsav8_setup_region(number, bar, lar);
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}
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static int __init pmsav8_setup_fixed(unsigned int number, phys_addr_t start,phys_addr_t end)
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{
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u32 bar, lar;
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if (!is_region_fixed(number))
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return -EINVAL;
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bar = start;
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lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);
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bar |= PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED;
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lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN;
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prsel_write(number);
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isb();
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if (prbar_read() != bar || prlar_read() != lar)
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return -EINVAL;
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/* Reserved region was set up early, we just need a record for secondaries */
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mpu_rgn_info.rgns[number].prbar = bar;
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mpu_rgn_info.rgns[number].prlar = lar;
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mpu_rgn_info.used++;
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return 0;
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}
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#ifndef CONFIG_CPU_V7M
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static int __init pmsav8_setup_vector(unsigned int number, phys_addr_t start,phys_addr_t end)
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{
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u32 bar, lar;
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if (number == PMSAv8_KERNEL_REGION)
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return -EINVAL;
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bar = start;
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lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);
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bar |= PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED;
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lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN;
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return __pmsav8_setup_region(number, bar, lar);
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}
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#endif
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void __init pmsav8_setup(void)
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{
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int i, err = 0;
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int region = PMSAv8_KERNEL_REGION;
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/* How many regions are supported ? */
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mpu_max_regions = __mpu_max_regions();
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/* RAM: single chunk of memory */
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add_range(mem, ARRAY_SIZE(mem), 0, memblock.memory.regions[0].base,
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memblock.memory.regions[0].base + memblock.memory.regions[0].size);
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/* IO: cover full 4G range */
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add_range(io, ARRAY_SIZE(io), 0, 0, 0xffffffff);
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/* RAM and IO: exclude kernel */
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subtract_range(mem, ARRAY_SIZE(mem), __pa(KERNEL_START), __pa(KERNEL_END));
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subtract_range(io, ARRAY_SIZE(io), __pa(KERNEL_START), __pa(KERNEL_END));
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#ifdef CONFIG_XIP_KERNEL
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/* RAM and IO: exclude xip */
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subtract_range(mem, ARRAY_SIZE(mem), CONFIG_XIP_PHYS_ADDR, __pa(_exiprom));
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subtract_range(io, ARRAY_SIZE(io), CONFIG_XIP_PHYS_ADDR, __pa(_exiprom));
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#endif
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#ifndef CONFIG_CPU_V7M
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/* RAM and IO: exclude vectors */
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subtract_range(mem, ARRAY_SIZE(mem), vectors_base, vectors_base + 2 * PAGE_SIZE);
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subtract_range(io, ARRAY_SIZE(io), vectors_base, vectors_base + 2 * PAGE_SIZE);
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#endif
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/* IO: exclude RAM */
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for (i = 0; i < ARRAY_SIZE(mem); i++)
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subtract_range(io, ARRAY_SIZE(io), mem[i].start, mem[i].end);
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/* Now program MPU */
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#ifdef CONFIG_XIP_KERNEL
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/* ROM */
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err |= pmsav8_setup_fixed(PMSAv8_XIP_REGION, CONFIG_XIP_PHYS_ADDR, __pa(_exiprom));
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#endif
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/* Kernel */
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err |= pmsav8_setup_fixed(region++, __pa(KERNEL_START), __pa(KERNEL_END));
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/* IO */
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for (i = 0; i < ARRAY_SIZE(io); i++) {
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if (!io[i].end)
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continue;
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err |= pmsav8_setup_io(region++, io[i].start, io[i].end);
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}
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/* RAM */
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for (i = 0; i < ARRAY_SIZE(mem); i++) {
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if (!mem[i].end)
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continue;
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err |= pmsav8_setup_ram(region++, mem[i].start, mem[i].end);
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}
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/* Vectors */
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#ifndef CONFIG_CPU_V7M
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err |= pmsav8_setup_vector(region++, vectors_base, vectors_base + 2 * PAGE_SIZE);
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#endif
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if (err)
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pr_warn("MPU region initialization failure! %d", err);
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else
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pr_info("Using ARM PMSAv8 Compliant MPU. Used %d of %d regions\n",
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mpu_rgn_info.used, mpu_max_regions);
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}
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