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Merge tag 'v3.14-rc4' into next

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Merge with Linux 3.14-rc4 to bring devm_request_any_context_irq().
This commit is contained in:
Dmitry Torokhov
2014-03-01 10:31:53 -08:00
parent 7fb45edba8 cfbf8d4857
commit 04421fe267
10279 changed files with 559472 additions and 218631 deletions
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6
include/linux/platform_data/asoc-ti-mcbsp.h
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@@ -1,6 +1,4 @@
/*
* arch/arm/plat-omap/include/mach/mcbsp.h
*
* Defines for Multi-Channel Buffered Serial Port
*
* Copyright (C) 2002 RidgeRun, Inc.
@@ -21,8 +19,8 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __ASM_ARCH_OMAP_MCBSP_H
#define __ASM_ARCH_OMAP_MCBSP_H
#ifndef __ASOC_TI_MCBSP_H
#define __ASOC_TI_MCBSP_H
#include <linux/spinlock.h>
#include <linux/clk.h>

9
include/linux/platform_data/asoc-ux500-msp.h
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@@ -10,16 +10,9 @@
#include <linux/platform_data/dma-ste-dma40.h>
enum msp_i2s_id {
MSP_I2S_0 = 0,
MSP_I2S_1,
MSP_I2S_2,
MSP_I2S_3,
};
/* Platform data structure for a MSP I2S-device */
struct msp_i2s_platform_data {
enum msp_i2s_id id;
int id;
struct stedma40_chan_cfg *msp_i2s_dma_rx;
struct stedma40_chan_cfg *msp_i2s_dma_tx;
};

9
include/linux/platform_data/clocksource-nomadik-mtu.h
View File

@@ -1,9 +0,0 @@
#ifndef __PLAT_MTU_H
#define __PLAT_MTU_H
void nmdk_timer_init(void __iomem *base, int irq);
void nmdk_clkevt_reset(void);
void nmdk_clksrc_reset(void);
#endif /* __PLAT_MTU_H */

1
include/linux/platform_data/davinci_asp.h
View File

@@ -92,6 +92,7 @@ enum {
MCASP_VERSION_1 = 0, /* DM646x */
MCASP_VERSION_2, /* DA8xx/OMAPL1x */
MCASP_VERSION_3, /* TI81xx/AM33xx */
MCASP_VERSION_4, /* DRA7xxx */
};
enum mcbsp_clk_input_pin {

5
include/linux/platform_data/dma-imx-sdma.h
View File

@@ -43,6 +43,11 @@ struct sdma_script_start_addrs {
s32 dptc_dvfs_addr;
s32 utra_addr;
s32 ram_code_start_addr;
/* End of v1 array */
s32 mcu_2_ssish_addr;
s32 ssish_2_mcu_addr;
s32 hdmi_dma_addr;
/* End of v2 array */
};
/**

1
include/linux/platform_data/dma-imx.h
View File

@@ -39,6 +39,7 @@ enum sdma_peripheral_type {
IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
IMX_DMATYPE_ASRC, /* ASRC */
IMX_DMATYPE_ESAI, /* ESAI */
IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
};
enum imx_dma_prio {

8
include/linux/platform_data/dma-mmp_tdma.h
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@@ -1,6 +1,4 @@
/*
* linux/arch/arm/mach-mmp/include/mach/sram.h
*
* SRAM Memory Management
*
* Copyright (c) 2011 Marvell Semiconductors Inc.
@@ -11,8 +9,8 @@
*
*/
#ifndef __ASM_ARCH_SRAM_H
#define __ASM_ARCH_SRAM_H
#ifndef __DMA_MMP_TDMA_H
#define __DMA_MMP_TDMA_H
#include <linux/genalloc.h>
@@ -32,4 +30,4 @@ struct sram_platdata {
extern struct gen_pool *sram_get_gpool(char *pool_name);
#endif /* __ASM_ARCH_SRAM_H */
#endif /* __DMA_MMP_TDMA_H */

6
include/linux/platform_data/dma-mv_xor.h
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@@ -1,11 +1,9 @@
/*
* arch/arm/plat-orion/include/plat/mv_xor.h
*
* Marvell XOR platform device data definition file.
*/
#ifndef __PLAT_MV_XOR_H
#define __PLAT_MV_XOR_H
#ifndef __DMA_MV_XOR_H
#define __DMA_MV_XOR_H
#include <linux/dmaengine.h>
#include <linux/mbus.h>

6
include/linux/platform_data/eth-netx.h
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@@ -1,6 +1,4 @@
/*
* arch/arm/mach-netx/include/mach/eth.h
*
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
@@ -17,8 +15,8 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef ASMARM_ARCH_ETH_H
#define ASMARM_ARCH_ETH_H
#ifndef __ETH_NETX_H
#define __ETH_NETX_H
struct netxeth_platform_data {
unsigned int xcno; /* number of xmac/xpec engine this eth uses */

3
include/linux/platform_data/gpio-davinci.h
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@@ -28,13 +28,12 @@ enum davinci_gpio_type {
struct davinci_gpio_platform_data {
u32 ngpio;
u32 gpio_unbanked;
u32 intc_irq_num;
};
struct davinci_gpio_controller {
struct gpio_chip chip;
int irq_base;
struct irq_domain *irq_domain;
/* Serialize access to GPIO registers */
spinlock_t lock;
void __iomem *regs;

50
include/linux/platform_data/gpio-lpc32xx.h Normal file
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@@ -0,0 +1,50 @@
/*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_GPIO_LPC32XX_H
#define __MACH_GPIO_LPC32XX_H
/*
* Note!
* Muxed GP pins need to be setup to the GP state in the board level
* code prior to using this driver.
* GPI pins : 28xP3 group
* GPO pins : 24xP3 group
* GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
*/
#define LPC32XX_GPIO_P0_MAX 8
#define LPC32XX_GPIO_P1_MAX 24
#define LPC32XX_GPIO_P2_MAX 13
#define LPC32XX_GPIO_P3_MAX 6
#define LPC32XX_GPI_P3_MAX 29
#define LPC32XX_GPO_P3_MAX 24
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
/*
* A specific GPIO can be selected with this macro
* ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
* See the LPC32x0 User's guide for GPIO group numbers
*/
#define LPC32XX_GPIO(x, y) ((x) + (y))
#endif /* __MACH_GPIO_LPC32XX_H */

10
include/linux/platform_data/hwmon-s3c.h
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@@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
*
/*
* Copyright 2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
@@ -11,8 +10,8 @@
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_ADC_HWMON_H
#define __ASM_ARCH_ADC_HWMON_H __FILE__
#ifndef __HWMON_S3C_H__
#define __HWMON_S3C_H__
/**
* s3c_hwmon_chcfg - channel configuration
@@ -47,5 +46,4 @@ struct s3c_hwmon_pdata {
*/
extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd);
#endif /* __ASM_ARCH_ADC_HWMON_H */
#endif /* __HWMON_S3C_H__ */

39
include/linux/platform_data/i2c-nomadik.h
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@@ -1,39 +0,0 @@
/*
* Copyright (C) 2009 ST-Ericsson
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*/
#ifndef __PDATA_I2C_NOMADIK_H
#define __PDATA_I2C_NOMADIK_H
enum i2c_freq_mode {
I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */
I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */
I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */
I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */
};
/**
* struct nmk_i2c_controller - client specific controller configuration
* @clk_freq: clock frequency for the operation mode
* @slsu: Slave data setup time in ns.
* The needed setup time for three modes of operation
* are 250ns, 100ns and 10ns respectively thus leading
* to the values of 14, 6, 2 for a 48 MHz i2c clk
* @tft: Tx FIFO Threshold in bytes
* @rft: Rx FIFO Threshold in bytes
* @timeout Slave response timeout(ms)
* @sm: speed mode
*/
struct nmk_i2c_controller {
u32 clk_freq;
unsigned short slsu;
unsigned char tft;
unsigned char rft;
int timeout;
enum i2c_freq_mode sm;
};
#endif /* __PDATA_I2C_NOMADIK_H */

8
include/linux/platform_data/leds-kirkwood-netxbig.h
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@@ -1,6 +1,4 @@
/*
* arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
*
* Platform data structure for netxbig LED driver
*
* This file is licensed under the terms of the GNU General Public
@@ -8,8 +6,8 @@
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_LEDS_NETXBIG_H
#define __MACH_LEDS_NETXBIG_H
#ifndef __LEDS_KIRKWOOD_NETXBIG_H
#define __LEDS_KIRKWOOD_NETXBIG_H
struct netxbig_gpio_ext {
unsigned *addr;
@@ -52,4 +50,4 @@ struct netxbig_led_platform_data {
int num_leds;
};
#endif /* __MACH_LEDS_NETXBIG_H */
#endif /* __LEDS_KIRKWOOD_NETXBIG_H */

8
include/linux/platform_data/leds-kirkwood-ns2.h
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@@ -1,6 +1,4 @@
/*
* arch/arm/mach-kirkwood/include/mach/leds-ns2.h
*
* Platform data structure for Network Space v2 LED driver
*
* This file is licensed under the terms of the GNU General Public
@@ -8,8 +6,8 @@
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_LEDS_NS2_H
#define __MACH_LEDS_NS2_H
#ifndef __LEDS_KIRKWOOD_NS2_H
#define __LEDS_KIRKWOOD_NS2_H
struct ns2_led {
const char *name;
@@ -23,4 +21,4 @@ struct ns2_led_platform_data {
struct ns2_led *leds;
};
#endif /* __MACH_LEDS_NS2_H */
#endif /* __LEDS_KIRKWOOD_NS2_H */

5
include/linux/platform_data/max197.h
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@@ -11,6 +11,9 @@
* For further information, see the Documentation/hwmon/max197 file.
*/
#ifndef _PDATA_MAX197_H
#define _PDATA_MAX197_H
/**
* struct max197_platform_data - MAX197 connectivity info
* @convert: Function used to start a conversion with control byte ctrl.
@@ -19,3 +22,5 @@
struct max197_platform_data {
int (*convert)(u8 ctrl);
};
#endif /* _PDATA_MAX197_H */

6
include/linux/platform_data/mfd-mcp-sa11x0.h
View File

@@ -1,14 +1,12 @@
/*
* arch/arm/mach-sa1100/include/mach/mcp.h
*
* Copyright (C) 2005 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_MCP_H
#define __ASM_ARM_ARCH_MCP_H
#ifndef __MFD_MCP_SA11X0_H
#define __MFD_MCP_SA11X0_H
#include <linux/types.h>

2
include/linux/platform_data/mtd-nand-omap2.h
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@@ -1,6 +1,4 @@
/*
* arch/arm/plat-omap/include/mach/nand.h
*
* Copyright (C) 2006 Micron Technology Inc.
*
* This program is free software; you can redistribute it and/or modify

3
include/linux/platform_data/mtd-nand-pxa3xx.h
View File

@@ -55,6 +55,9 @@ struct pxa3xx_nand_platform_data {
/* indicate how many chip selects will be used */
int num_cs;
/* use an flash-based bad block table */
bool flash_bbt;
const struct mtd_partition *parts[NUM_CHIP_SELECT];
unsigned int nr_parts[NUM_CHIP_SELECT];

2
include/linux/platform_data/mtd-onenand-omap2.h
View File

@@ -1,6 +1,4 @@
/*
* arch/arm/plat-omap/include/mach/onenand.h
*
* Copyright (C) 2006 Nokia Corporation
* Author: Juha Yrjola
*

6
include/linux/platform_data/mtd-orion_nand.h
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@@ -1,13 +1,11 @@
/*
* arch/arm/plat-orion/include/plat/orion_nand.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_ORION_NAND_H
#define __PLAT_ORION_NAND_H
#ifndef __MTD_ORION_NAND_H
#define __MTD_ORION_NAND_H
/*
* Device bus NAND private data

242
include/linux/platform_data/pinctrl-nomadik.h
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@@ -1,242 +0,0 @@
/*
* Structures and registers for GPIO access in the Nomadik SoC
*
* Copyright (C) 2008 STMicroelectronics
* Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
* Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_NOMADIK_GPIO
#define __PLAT_NOMADIK_GPIO
/*
* pin configurations are represented by 32-bit integers:
*
* bit 0.. 8 - Pin Number (512 Pins Maximum)
* bit 9..10 - Alternate Function Selection
* bit 11..12 - Pull up/down state
* bit 13 - Sleep mode behaviour
* bit 14 - Direction
* bit 15 - Value (if output)
* bit 16..18 - SLPM pull up/down state
* bit 19..20 - SLPM direction
* bit 21..22 - SLPM Value (if output)
* bit 23..25 - PDIS value (if input)
* bit 26 - Gpio mode
* bit 27 - Sleep mode
*
* to facilitate the definition, the following macros are provided
*
* PIN_CFG_DEFAULT - default config (0):
* pull up/down = disabled
* sleep mode = input/wakeup
* direction = input
* value = low
* SLPM direction = same as normal
* SLPM pull = same as normal
* SLPM value = same as normal
*
* PIN_CFG - default config with alternate function
*/
typedef unsigned long pin_cfg_t;
#define PIN_NUM_MASK 0x1ff
#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
#define PIN_ALT_SHIFT 9
#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
#define PIN_PULL_SHIFT 11
#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
#define PIN_SLPM_SHIFT 13
#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
/* These two replace the above in DB8500v2+ */
#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
#define PIN_DIR_SHIFT 14
#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
#define PIN_VAL_SHIFT 15
#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
#define PIN_SLPM_PULL_SHIFT 16
#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL(x) \
(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL_NONE \
((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL_UP \
((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL_DOWN \
((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_DIR_SHIFT 19
#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_DIR(x) \
(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_VAL_SHIFT 21
#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
#define PIN_SLPM_VAL(x) \
(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
#define PIN_SLPM_PDIS_SHIFT 23
#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
#define PIN_SLPM_PDIS(x) \
(((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
#define PIN_LOWEMI_SHIFT 25
#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
#define PIN_GPIOMODE_SHIFT 26
#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
#define PIN_SLEEPMODE_SHIFT 27
#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
#define PIN_CFG_DEFAULT (0)
#define PIN_CFG(num, alt) \
(PIN_CFG_DEFAULT |\
(PIN_NUM(num) | PIN_##alt))
#define PIN_CFG_INPUT(num, alt, pull) \
(PIN_CFG_DEFAULT |\
(PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
#define PIN_CFG_OUTPUT(num, alt, val) \
(PIN_CFG_DEFAULT |\
(PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
/*
* "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
* the "gpio" namespace for generic and cross-machine functions
*/
#define GPIO_BLOCK_SHIFT 5
#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
/* Register in the logic block */
#define NMK_GPIO_DAT 0x00
#define NMK_GPIO_DATS 0x04
#define NMK_GPIO_DATC 0x08
#define NMK_GPIO_PDIS 0x0c
#define NMK_GPIO_DIR 0x10
#define NMK_GPIO_DIRS 0x14
#define NMK_GPIO_DIRC 0x18
#define NMK_GPIO_SLPC 0x1c
#define NMK_GPIO_AFSLA 0x20
#define NMK_GPIO_AFSLB 0x24
#define NMK_GPIO_LOWEMI 0x28
#define NMK_GPIO_RIMSC 0x40
#define NMK_GPIO_FIMSC 0x44
#define NMK_GPIO_IS 0x48
#define NMK_GPIO_IC 0x4c
#define NMK_GPIO_RWIMSC 0x50
#define NMK_GPIO_FWIMSC 0x54
#define NMK_GPIO_WKS 0x58
/* These appear in DB8540 and later ASICs */
#define NMK_GPIO_EDGELEVEL 0x5C
#define NMK_GPIO_LEVEL 0x60
/* Alternate functions: function C is set in hw by setting both A and B */
#define NMK_GPIO_ALT_GPIO 0
#define NMK_GPIO_ALT_A 1
#define NMK_GPIO_ALT_B 2
#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
#define NMK_GPIO_ALT_CX_SHIFT 2
#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
/* Pull up/down values */
enum nmk_gpio_pull {
NMK_GPIO_PULL_NONE,
NMK_GPIO_PULL_UP,
NMK_GPIO_PULL_DOWN,
};
/* Sleep mode */
enum nmk_gpio_slpm {
NMK_GPIO_SLPM_INPUT,
NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
NMK_GPIO_SLPM_NOCHANGE,
NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
};
/*
* Platform data to register a block: only the initial gpio/irq number.
*/
struct nmk_gpio_platform_data {
char *name;
int first_gpio;
int first_irq;
int num_gpio;
u32 (*get_secondary_status)(unsigned int bank);
void (*set_ioforce)(bool enable);
bool supports_sleepmode;
};
#endif /* __PLAT_NOMADIK_GPIO */

3
include/linux/platform_data/pn544.h
View File

@@ -16,8 +16,7 @@
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _PN544_H_

5
include/linux/platform_data/sht15.h
View File

@@ -12,6 +12,9 @@
* For further information, see the Documentation/hwmon/sht15 file.
*/
#ifndef _PDATA_SHT15_H
#define _PDATA_SHT15_H
/**
* struct sht15_platform_data - sht15 connectivity info
* @gpio_data: no. of gpio to which bidirectional data line is
@@ -31,3 +34,5 @@ struct sht15_platform_data {
bool no_otp_reload;
bool low_resolution;
};
#endif /* _PDATA_SHT15_H */

16
include/linux/platform_data/si5351.h
View File

@@ -7,20 +7,6 @@
struct clk;
/**
* enum si5351_variant - SiLabs Si5351 chip variant
* @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
* @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
* @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
* @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
*/
enum si5351_variant {
SI5351_VARIANT_A = 1,
SI5351_VARIANT_A3 = 2,
SI5351_VARIANT_B = 3,
SI5351_VARIANT_C = 4,
};
/**
* enum si5351_pll_src - Si5351 pll clock source
* @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config
@@ -115,14 +101,12 @@ struct si5351_clkout_config {
/**
* struct si5351_platform_data - Platform data for the Si5351 clock driver
* @variant: Si5351 chip variant
* @clk_xtal: xtal input clock
* @clk_clkin: clkin input clock
* @pll_src: array of pll source clock setting
* @clkout: array of clkout configuration
*/
struct si5351_platform_data {
enum si5351_variant variant;
struct clk *clk_xtal;
struct clk *clk_clkin;
enum si5351_pll_src pll_src[2];

8
include/linux/platform_data/spi-nuc900.h
View File

@@ -1,6 +1,4 @@
/*
* arch/arm/mach-w90x900/include/mach/nuc900_spi.h
*
* Copyright (c) 2009 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
@@ -11,8 +9,8 @@
*
*/
#ifndef __ASM_ARCH_SPI_H
#define __ASM_ARCH_SPI_H
#ifndef __SPI_NUC900_H
#define __SPI_NUC900_H
extern void mfp_set_groupg(struct device *dev, const char *subname);
@@ -32,4 +30,4 @@ struct nuc900_spi_chip {
unsigned char bits_per_word;
};
#endif /* __ASM_ARCH_SPI_H */
#endif /* __SPI_NUC900_H */

6
include/linux/platform_data/usb-ehci-orion.h
View File

@@ -1,13 +1,11 @@
/*
* arch/arm/plat-orion/include/plat/ehci-orion.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_EHCI_ORION_H
#define __PLAT_EHCI_ORION_H
#ifndef __USB_EHCI_ORION_H
#define __USB_EHCI_ORION_H
#include <linux/mbus.h>

53
include/linux/platform_data/usb-omap1.h Normal file
View File

@@ -0,0 +1,53 @@
/*
* Platform data for OMAP1 USB
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive for
* more details.
*/
#ifndef __LINUX_USB_OMAP1_H
#define __LINUX_USB_OMAP1_H
#include <linux/platform_device.h>
struct omap_usb_config {
/* Configure drivers according to the connectors on your board:
* - "A" connector (rectagular)
* ... for host/OHCI use, set "register_host".
* - "B" connector (squarish) or "Mini-B"
* ... for device/gadget use, set "register_dev".
* - "Mini-AB" connector (very similar to Mini-B)
* ... for OTG use as device OR host, initialize "otg"
*/
unsigned register_host:1;
unsigned register_dev:1;
u8 otg; /* port number, 1-based: usb1 == 2 */
const char *extcon; /* extcon device for OTG */
u8 hmc_mode;
/* implicitly true if otg: host supports remote wakeup? */
u8 rwc;
/* signaling pins used to talk to transceiver on usbN:
* 0 == usbN unused
* 2 == usb0-only, using internal transceiver
* 3 == 3 wire bidirectional
* 4 == 4 wire bidirectional
* 6 == 6 wire unidirectional (or TLL)
*/
u8 pins[3];
struct platform_device *udc_device;
struct platform_device *ohci_device;
struct platform_device *otg_device;
u32 (*usb0_init)(unsigned nwires, unsigned is_device);
u32 (*usb1_init)(unsigned nwires);
u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
int (*ocpi_enable)(void);
};
#endif /* __LINUX_USB_OMAP1_H */

10
include/linux/platform_data/video-ep93xx.h
View File

@@ -1,9 +1,5 @@
/*
* arch/arm/mach-ep93xx/include/mach/fb.h
*/
#ifndef __ASM_ARCH_EP93XXFB_H
#define __ASM_ARCH_EP93XXFB_H
#ifndef __VIDEO_EP93XX_H
#define __VIDEO_EP93XX_H
struct platform_device;
struct fb_videomode;
@@ -53,4 +49,4 @@ struct ep93xxfb_mach_info {
void (*blank)(int blank_mode, struct fb_info *info);
};
#endif /* __ASM_ARCH_EP93XXFB_H */
#endif /* __VIDEO_EP93XX_H */

3
include/linux/platform_data/video-msm_fb.h
View File

@@ -1,5 +1,4 @@
/* arch/arm/mach-msm/include/mach/msm_fb.h
*
/*
* Internal shared definitions for various MSM framebuffer parts.
*
* Copyright (C) 2007 Google Incorporated

2
include/linux/platform_data/video-pxafb.h
View File

@@ -1,6 +1,4 @@
/*
* arch/arm/mach-pxa/include/mach/pxafb.h
*
* Support for the xscale frame buffer.
*
* Author: Jean-Frederic Clere

2
include/linux/platform_data/vsp1.h
View File

@@ -14,6 +14,8 @@
#define __PLATFORM_VSP1_H__
#define VSP1_HAS_LIF (1 << 0)
#define VSP1_HAS_LUT (1 << 1)
#define VSP1_HAS_SRU (1 << 2)
struct vsp1_platform_data {
unsigned int features;