Merge tag 'drm-intel-next-2014-10-24' of git://anongit.freedesktop.org/drm-intel into drm-next
- suspend/resume/freeze/thaw unification from Imre - wa list improvements from Mika&Arun - display pll precomputation from Ander Conselvan, this removed the last ->mode_set callbacks, a big step towards implementing atomic modesets - more kerneldoc for the interrupt code - 180 rotation for cursors (Ville&Sonika) - ULT/ULX feature check macros cleaned up thanks to Damien - piles and piles of fixes all over, bug team seems to work! * tag 'drm-intel-next-2014-10-24' of git://anongit.freedesktop.org/drm-intel: (61 commits) drm/i915: Update DRIVER_DATE to 20141024 drm/i915: add comments on what stage a given PM handler is called drm/i915: unify switcheroo and legacy suspend/resume handlers drm/i915: add poweroff_late handler drm/i915: sanitize suspend/resume helper function names drm/i915: unify S3 and S4 suspend/resume handlers drm/i915: disable/re-enable PCI device around S4 freeze/thaw drm/i915: enable output polling during S4 thaw drm/i915: check for GT faults in all resume handlers and driver load time drm/i915: remove unused restore_gtt_mappings optimization during suspend drm/i915: fix S4 suspend while switcheroo state is off drm/i915: vlv: fix switcheroo/legacy suspend/resume drm/i915: propagate error from legacy resume handler drm/i915: unify legacy S3 suspend and S4 freeze handlers drm/i915: factor out i915_drm_suspend_late drm/i915: Emit even number of dwords when emitting LRIs drm/i915: Add rotation support for cursor plane (v5) drm/i915: Correctly reject invalid flags for wait_ioctl drm/i915: use macros to assign mmio access functions drm/i915: only run hsw_power_well_post_enable when really needed ...
This commit is contained in:
Dave Airlie
@@ -665,80 +665,108 @@ err:
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return ret;
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}
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static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
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u32 addr, u32 value)
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static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
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{
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int ret, i;
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_workarounds *w = &dev_priv->workarounds;
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if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
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return;
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if (WARN_ON(w->count == 0))
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return 0;
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intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit(ring, addr);
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intel_ring_emit(ring, value);
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dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
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dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
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/* value is updated with the status of remaining bits of this
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* register when it is read from debugfs file
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*/
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dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
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dev_priv->num_wa_regs++;
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return;
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}
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static int bdw_init_workarounds(struct intel_engine_cs *ring)
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{
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int ret;
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* workarounds applied in this fn are part of register state context,
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* they need to be re-initialized followed by gpu reset, suspend/resume,
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* module reload.
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*/
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dev_priv->num_wa_regs = 0;
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memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
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/*
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* update the number of dwords required based on the
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* actual number of workarounds applied
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*/
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ret = intel_ring_begin(ring, 18);
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ring->gpu_caches_dirty = true;
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ret = intel_ring_flush_all_caches(ring);
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if (ret)
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return ret;
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ret = intel_ring_begin(ring, (w->count * 2 + 2));
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
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for (i = 0; i < w->count; i++) {
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intel_ring_emit(ring, w->reg[i].addr);
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intel_ring_emit(ring, w->reg[i].value);
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}
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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ring->gpu_caches_dirty = true;
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ret = intel_ring_flush_all_caches(ring);
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if (ret)
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return ret;
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DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
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return 0;
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}
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static int wa_add(struct drm_i915_private *dev_priv,
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const u32 addr, const u32 val, const u32 mask)
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{
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const u32 idx = dev_priv->workarounds.count;
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if (WARN_ON(idx >= I915_MAX_WA_REGS))
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return -ENOSPC;
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dev_priv->workarounds.reg[idx].addr = addr;
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dev_priv->workarounds.reg[idx].value = val;
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dev_priv->workarounds.reg[idx].mask = mask;
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dev_priv->workarounds.count++;
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return 0;
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}
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#define WA_REG(addr, val, mask) { \
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const int r = wa_add(dev_priv, (addr), (val), (mask)); \
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if (r) \
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return r; \
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}
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#define WA_SET_BIT_MASKED(addr, mask) \
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WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
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#define WA_CLR_BIT_MASKED(addr, mask) \
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WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
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#define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
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#define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
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#define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
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static int bdw_init_workarounds(struct intel_engine_cs *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* WaDisablePartialInstShootdown:bdw */
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/* WaDisableThreadStallDopClockGating:bdw */
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/* FIXME: Unclear whether we really need this on production bdw. */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
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| STALL_DOP_GATING_DISABLE));
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/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
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STALL_DOP_GATING_DISABLE);
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/* WaDisableDopClockGating:bdw May not be needed for production */
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intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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/* WaDisableDopClockGating:bdw */
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WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
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DOP_CLOCK_GATING_DISABLE);
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intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
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WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
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GEN8_SAMPLER_POWER_BYPASS_DIS);
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/* Use Force Non-Coherent whenever executing a 3D context. This is a
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* workaround for for a possible hang in the unlikely event a TLB
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* invalidation occurs during a PSD flush.
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*/
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/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
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intel_ring_emit_wa(ring, HDC_CHICKEN0,
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_MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT |
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(IS_BDW_GT3(dev) ?
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HDC_FENCE_DEST_SLM_DISABLE : 0)
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));
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WA_SET_BIT_MASKED(HDC_CHICKEN0,
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HDC_FORCE_NON_COHERENT |
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(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
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/* Wa4x4STCOptimizationDisable:bdw */
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intel_ring_emit_wa(ring, CACHE_MODE_1,
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_MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
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WA_SET_BIT_MASKED(CACHE_MODE_1,
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GEN8_4x4_STC_OPTIMIZATION_DISABLE);
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/*
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* BSpec recommends 8x4 when MSAA is used,
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@@ -748,52 +776,50 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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intel_ring_emit_wa(ring, GEN7_GT_MODE,
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GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
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intel_ring_advance(ring);
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DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
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dev_priv->num_wa_regs);
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WA_SET_BIT_MASKED(GEN7_GT_MODE,
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GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
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return 0;
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}
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static int chv_init_workarounds(struct intel_engine_cs *ring)
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{
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int ret;
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* workarounds applied in this fn are part of register state context,
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* they need to be re-initialized followed by gpu reset, suspend/resume,
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* module reload.
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*/
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dev_priv->num_wa_regs = 0;
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memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
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ret = intel_ring_begin(ring, 12);
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if (ret)
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return ret;
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/* WaDisablePartialInstShootdown:chv */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
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/* WaDisableThreadStallDopClockGating:chv */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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STALL_DOP_GATING_DISABLE);
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/* WaDisableDopClockGating:chv (pre-production hw) */
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intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
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DOP_CLOCK_GATING_DISABLE);
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/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
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intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
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WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
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GEN8_SAMPLER_POWER_BYPASS_DIS);
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intel_ring_advance(ring);
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return 0;
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}
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static int init_workarounds_ring(struct intel_engine_cs *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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WARN_ON(ring->id != RCS);
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dev_priv->workarounds.count = 0;
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if (IS_BROADWELL(dev))
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return bdw_init_workarounds(ring);
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if (IS_CHERRYVIEW(dev))
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return chv_init_workarounds(ring);
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return 0;
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}
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@@ -853,7 +879,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
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if (HAS_L3_DPF(dev))
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I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
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return ret;
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return init_workarounds_ring(ring);
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}
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static void render_ring_cleanup(struct intel_engine_cs *ring)
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@@ -2299,10 +2325,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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dev_priv->semaphore_obj = obj;
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}
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}
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if (IS_CHERRYVIEW(dev))
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ring->init_context = chv_init_workarounds;
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else
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ring->init_context = bdw_init_workarounds;
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ring->init_context = intel_ring_workarounds_emit;
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ring->add_request = gen6_add_request;
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ring->flush = gen8_render_ring_flush;
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ring->irq_get = gen8_ring_get_irq;
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