Merge tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"This time we have a very typical update which is mostly fixes and
updates to drivers and no new drivers.
- the biggest change is coming from Peter for edma cleanup which even
caused some last minute regression, things seem settled now
- idma64 and dw updates
- iotdma updates
- module autoload fixes for various drivers
- scatter gather support for hdmac"
* tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (77 commits)
dmaengine: edma: Add dummy driver skeleton for edma3-tptc
Revert "ARM: DTS: am33xx: Use the new DT bindings for the eDMA3"
Revert "ARM: DTS: am437x: Use the new DT bindings for the eDMA3"
dmaengine: dw: some Intel devices has no memcpy support
dmaengine: dw: platform: provide platform data for Intel
dmaengine: dw: don't override platform data with autocfg
dmaengine: hdmac: Add scatter-gathered memset support
dmaengine: hdmac: factorise memset descriptor allocation
dmaengine: virt-dma: Fix kernel-doc annotations
ARM: DTS: am437x: Use the new DT bindings for the eDMA3
ARM: DTS: am33xx: Use the new DT bindings for the eDMA3
dmaengine: edma: New device tree binding
dmaengine: Kconfig: edma: Select TI_DMA_CROSSBAR in case of ARCH_OMAP
dmaengine: ti-dma-crossbar: Add support for crossbar on AM33xx/AM43xx
dmaengine: edma: Merge the of parsing functions
dmaengine: edma: Do not allocate memory for edma_rsv_info in case of DT boot
dmaengine: edma: Refactor the dma device and channel struct initialization
dmaengine: edma: Get qDMA channel information from HW also
dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq
dmaengine: edma: Correct PaRAM access function names (_parm_ to _param_)
...
This commit is contained in:
Linus Torvalds
@@ -163,7 +163,7 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
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/*----------------------------------------------------------------------*/
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static inline unsigned int dwc_fast_fls(unsigned long long v)
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static inline unsigned int dwc_fast_ffs(unsigned long long v)
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{
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/*
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* We can be a lot more clever here, but this should take care
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@@ -712,7 +712,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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dw->data_width[dwc->dst_master]);
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src_width = dst_width = min_t(unsigned int, data_width,
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dwc_fast_fls(src | dest | len));
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dwc_fast_ffs(src | dest | len));
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ctllo = DWC_DEFAULT_CTLLO(chan)
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| DWC_CTLL_DST_WIDTH(dst_width)
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@@ -791,7 +791,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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switch (direction) {
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case DMA_MEM_TO_DEV:
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reg_width = __fls(sconfig->dst_addr_width);
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reg_width = __ffs(sconfig->dst_addr_width);
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reg = sconfig->dst_addr;
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ctllo = (DWC_DEFAULT_CTLLO(chan)
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| DWC_CTLL_DST_WIDTH(reg_width)
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@@ -811,7 +811,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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len = sg_dma_len(sg);
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mem_width = min_t(unsigned int,
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data_width, dwc_fast_fls(mem | len));
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data_width, dwc_fast_ffs(mem | len));
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slave_sg_todev_fill_desc:
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desc = dwc_desc_get(dwc);
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@@ -848,7 +848,7 @@ slave_sg_todev_fill_desc:
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}
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break;
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case DMA_DEV_TO_MEM:
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reg_width = __fls(sconfig->src_addr_width);
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reg_width = __ffs(sconfig->src_addr_width);
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reg = sconfig->src_addr;
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ctllo = (DWC_DEFAULT_CTLLO(chan)
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| DWC_CTLL_SRC_WIDTH(reg_width)
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@@ -868,7 +868,7 @@ slave_sg_todev_fill_desc:
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len = sg_dma_len(sg);
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mem_width = min_t(unsigned int,
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data_width, dwc_fast_fls(mem | len));
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data_width, dwc_fast_ffs(mem | len));
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slave_sg_fromdev_fill_desc:
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desc = dwc_desc_get(dwc);
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@@ -1499,9 +1499,8 @@ EXPORT_SYMBOL(dw_dma_cyclic_free);
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int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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{
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struct dw_dma *dw;
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bool autocfg;
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bool autocfg = false;
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unsigned int dw_params;
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unsigned int nr_channels;
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unsigned int max_blk_size = 0;
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int err;
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int i;
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@@ -1515,33 +1514,42 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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pm_runtime_get_sync(chip->dev);
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dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
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autocfg = dw_params >> DW_PARAMS_EN & 0x1;
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if (!pdata) {
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dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
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dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
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dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
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autocfg = dw_params >> DW_PARAMS_EN & 1;
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if (!autocfg) {
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err = -EINVAL;
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goto err_pdata;
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}
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if (!pdata && autocfg) {
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pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata) {
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err = -ENOMEM;
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goto err_pdata;
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}
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/* Get hardware configuration parameters */
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pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
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pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
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for (i = 0; i < pdata->nr_masters; i++) {
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pdata->data_width[i] =
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(dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
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}
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max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
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/* Fill platform data with the default values */
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pdata->is_private = true;
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pdata->is_memcpy = true;
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pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
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pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
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} else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
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} else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
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err = -EINVAL;
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goto err_pdata;
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}
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if (autocfg)
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nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
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else
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nr_channels = pdata->nr_channels;
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dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
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dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
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GFP_KERNEL);
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if (!dw->chan) {
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err = -ENOMEM;
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@@ -1549,22 +1557,12 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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}
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/* Get hardware configuration parameters */
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if (autocfg) {
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max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
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dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
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for (i = 0; i < dw->nr_masters; i++) {
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dw->data_width[i] =
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(dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
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}
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} else {
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dw->nr_masters = pdata->nr_masters;
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for (i = 0; i < dw->nr_masters; i++)
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dw->data_width[i] = pdata->data_width[i];
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}
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dw->nr_masters = pdata->nr_masters;
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for (i = 0; i < dw->nr_masters; i++)
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dw->data_width[i] = pdata->data_width[i];
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/* Calculate all channel mask before DMA setup */
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dw->all_chan_mask = (1 << nr_channels) - 1;
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dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
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/* Force dma off, just in case */
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dw_dma_off(dw);
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@@ -1589,7 +1587,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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goto err_pdata;
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INIT_LIST_HEAD(&dw->dma.channels);
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for (i = 0; i < nr_channels; i++) {
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for (i = 0; i < pdata->nr_channels; i++) {
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struct dw_dma_chan *dwc = &dw->chan[i];
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dwc->chan.device = &dw->dma;
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@@ -1602,7 +1600,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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/* 7 is highest priority & 0 is lowest. */
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if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
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dwc->priority = nr_channels - i - 1;
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dwc->priority = pdata->nr_channels - i - 1;
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else
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dwc->priority = i;
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@@ -1656,10 +1654,13 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
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dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
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dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
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/* Set capabilities */
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dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
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if (pdata->is_private)
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dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
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if (pdata->is_memcpy)
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dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
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dw->dma.dev = chip->dev;
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dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
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dw->dma.device_free_chan_resources = dwc_free_chan_resources;
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@@ -1687,7 +1688,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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goto err_dma_register;
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dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
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nr_channels);
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pdata->nr_channels);
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pm_runtime_put_sync_suspend(chip->dev);
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@@ -15,12 +15,6 @@
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#include "internal.h"
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static struct dw_dma_platform_data dw_pci_pdata = {
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.is_private = 1,
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.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
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.chan_priority = CHAN_PRIORITY_ASCENDING,
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};
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static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
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{
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struct dw_dma_chip *chip;
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@@ -101,19 +95,19 @@ static const struct dev_pm_ops dw_pci_dev_pm_ops = {
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static const struct pci_device_id dw_pci_id_table[] = {
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/* Medfield */
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{ PCI_VDEVICE(INTEL, 0x0827), (kernel_ulong_t)&dw_pci_pdata },
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{ PCI_VDEVICE(INTEL, 0x0830), (kernel_ulong_t)&dw_pci_pdata },
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{ PCI_VDEVICE(INTEL, 0x0827) },
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{ PCI_VDEVICE(INTEL, 0x0830) },
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/* BayTrail */
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{ PCI_VDEVICE(INTEL, 0x0f06), (kernel_ulong_t)&dw_pci_pdata },
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{ PCI_VDEVICE(INTEL, 0x0f40), (kernel_ulong_t)&dw_pci_pdata },
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{ PCI_VDEVICE(INTEL, 0x0f06) },
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{ PCI_VDEVICE(INTEL, 0x0f40) },
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/* Braswell */
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{ PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_pdata },
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{ PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_pdata },
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{ PCI_VDEVICE(INTEL, 0x2286) },
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{ PCI_VDEVICE(INTEL, 0x22c0) },
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/* Haswell */
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{ PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_pdata },
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{ PCI_VDEVICE(INTEL, 0x9c60) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, dw_pci_id_table);
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@@ -155,6 +155,7 @@ static int dw_probe(struct platform_device *pdev)
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struct dw_dma_chip *chip;
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struct device *dev = &pdev->dev;
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struct resource *mem;
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const struct acpi_device_id *id;
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struct dw_dma_platform_data *pdata;
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int err;
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@@ -178,6 +179,11 @@ static int dw_probe(struct platform_device *pdev)
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pdata = dev_get_platdata(dev);
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if (!pdata)
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pdata = dw_dma_parse_dt(pdev);
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if (!pdata && has_acpi_companion(dev)) {
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id = acpi_match_device(dev->driver->acpi_match_table, dev);
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if (id)
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pdata = (struct dw_dma_platform_data *)id->driver_data;
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}
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chip->dev = dev;
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@@ -246,8 +252,17 @@ MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
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#endif
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#ifdef CONFIG_ACPI
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static struct dw_dma_platform_data dw_dma_acpi_pdata = {
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.nr_channels = 8,
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.is_private = true,
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.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
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.chan_priority = CHAN_PRIORITY_ASCENDING,
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.block_size = 4095,
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.nr_masters = 2,
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};
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static const struct acpi_device_id dw_dma_acpi_id_table[] = {
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{ "INTL9C60", 0 },
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{ "INTL9C60", (kernel_ulong_t)&dw_dma_acpi_pdata },
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
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