drm/radeon: split PT setup in more functions
Move the decision what to use into the common VM code. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
committed by
Alex Deucher
Alex Deucher
parent
5a341be27f
commit
03f62abd11
@@ -307,7 +307,43 @@ bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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}
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/**
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* cayman_dma_vm_set_page - update the page tables using the DMA
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* cayman_dma_vm_copy_pages - update PTEs by copying them from the GART
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @src: src addr where to copy from
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* @count: number of page entries to update
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*
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* Update PTEs by copying them from the GART using the DMA (cayman/TN).
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*/
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void cayman_dma_vm_copy_pages(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe, uint64_t src,
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unsigned count)
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{
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unsigned ndw;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
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0, 0, ndw);
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ib->ptr[ib->length_dw++] = lower_32_bits(pe);
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ib->ptr[ib->length_dw++] = lower_32_bits(src);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
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pe += ndw * 4;
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src += ndw * 4;
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count -= ndw / 2;
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}
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}
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/**
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* cayman_dma_vm_write_pages - update PTEs by writing them manually
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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@@ -315,90 +351,103 @@ bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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* @flags: hw access flags
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*
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* Update the page tables using the DMA (cayman/TN).
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* Update PTEs by writing them manually using the DMA (cayman/TN).
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*/
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void cayman_dma_vm_set_page(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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void cayman_dma_vm_write_pages(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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{
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uint64_t value;
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unsigned ndw;
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trace_radeon_vm_set_page(pe, addr, count, incr, flags);
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
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uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
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0, 0, ndw);
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ib->ptr[ib->length_dw++] = lower_32_bits(pe);
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ib->ptr[ib->length_dw++] = lower_32_bits(src);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
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pe += ndw * 4;
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src += ndw * 4;
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count -= ndw / 2;
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}
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} else if ((flags & R600_PTE_SYSTEM) || (count == 1)) {
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & R600_PTE_SYSTEM) {
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value = radeon_vm_map_gart(rdev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & R600_PTE_VALID) {
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value = addr;
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} else {
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value = 0;
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}
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addr += incr;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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}
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}
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} else {
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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if (flags & R600_PTE_VALID)
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE,
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0, 0, ndw);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & R600_PTE_SYSTEM) {
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value = radeon_vm_map_gart(rdev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & R600_PTE_VALID) {
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value = addr;
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else
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} else {
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value = 0;
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/* for physically contiguous pages (vram) */
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ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
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ib->ptr[ib->length_dw++] = pe; /* dst addr */
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = flags; /* mask */
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ib->ptr[ib->length_dw++] = 0;
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ib->ptr[ib->length_dw++] = value; /* value */
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}
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addr += incr;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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ib->ptr[ib->length_dw++] = incr; /* increment size */
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ib->ptr[ib->length_dw++] = 0;
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pe += ndw * 4;
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addr += (ndw / 2) * incr;
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count -= ndw / 2;
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}
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}
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}
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/**
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* cayman_dma_vm_set_pages - update the page tables using the DMA
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Update the page tables using the DMA (cayman/TN).
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*/
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void cayman_dma_vm_set_pages(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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{
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uint64_t value;
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unsigned ndw;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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if (flags & R600_PTE_VALID)
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value = addr;
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else
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value = 0;
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/* for physically contiguous pages (vram) */
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ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
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ib->ptr[ib->length_dw++] = pe; /* dst addr */
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = flags; /* mask */
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ib->ptr[ib->length_dw++] = 0;
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ib->ptr[ib->length_dw++] = value; /* value */
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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ib->ptr[ib->length_dw++] = incr; /* increment size */
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ib->ptr[ib->length_dw++] = 0;
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pe += ndw * 4;
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addr += (ndw / 2) * incr;
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count -= ndw / 2;
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}
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}
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/**
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* cayman_dma_vm_pad_ib - pad the IB to the required number of dw
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*
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* @ib: indirect buffer to fill with padding
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*
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*/
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void cayman_dma_vm_pad_ib(struct radeon_ib *ib)
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{
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while (ib->length_dw & 0x7)
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
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}
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