x86/asm/tsc: Add rdtsc_ordered() and use it in trivial call sites
rdtsc_barrier(); rdtsc() is an unnecessary mouthful and requires more thought than should be necessary. Add an rdtsc_ordered() helper and replace the trivial call sites with it. This should not change generated code. The duplication of the fence asm is temporary. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Len Brown <lenb@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: kvm ML <kvm@vger.kernel.org> Link: http://lkml.kernel.org/r/dddbf98a2af53312e9aa73a5a2b1622fe5d6f52b.1434501121.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@@ -175,20 +175,8 @@ static notrace cycle_t vread_pvclock(int *mode)
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notrace static cycle_t vread_tsc(void)
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{
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cycle_t ret;
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u64 last;
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/*
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* Empirically, a fence (of type that depends on the CPU)
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* before rdtsc is enough to ensure that rdtsc is ordered
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* with respect to loads. The various CPU manuals are unclear
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* as to whether rdtsc can be reordered with later loads,
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* but no one has ever seen it happen.
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*/
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rdtsc_barrier();
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ret = (cycle_t)rdtsc();
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last = gtod->cycle_last;
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cycle_t ret = (cycle_t)rdtsc_ordered();
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u64 last = gtod->cycle_last;
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if (likely(ret >= last))
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return ret;
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