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drm/pl111: Register the clock divider and use it.

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This is required for the panel to work on bcm911360, where CLCDCLK is
the fixed 200Mhz AXI41 clock.  The rate set is still passed up to the
CLCDCLK, for platforms that have a settable rate on that one.

v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
    COMMON_CLK.
v3: Mark the clk_ops static (caught by Stephen).

Signed-off-by: Eric Anholt <eric@anholt.net>
Link: http://patchwork.freedesktop.org/patch/msgid/20170508193348.30236-1-eric@anholt.net
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Eric Anholt
2017-05-08 12:33:48 -07:00
parent 2098105ec6
commit 032838f9cb
5 changed files with 163 additions and 24 deletions
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5
include/linux/amba/clcd-regs.h
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@@ -39,12 +39,17 @@
#define CLCD_PALL 0x00000200
#define CLCD_PALETTE 0x00000200
#define TIM2_PCD_LO_MASK GENMASK(4, 0)
#define TIM2_PCD_LO_BITS 5
#define TIM2_CLKSEL (1 << 5)
#define TIM2_IVS (1 << 11)
#define TIM2_IHS (1 << 12)
#define TIM2_IPC (1 << 13)
#define TIM2_IOE (1 << 14)
#define TIM2_BCD (1 << 26)
#define TIM2_PCD_HI_MASK GENMASK(31, 27)
#define TIM2_PCD_HI_BITS 5
#define TIM2_PCD_HI_SHIFT 27
#define CNTL_LCDEN (1 << 0)
#define CNTL_LCDBPP1 (0 << 1)