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drm/pl111: Register the clock divider and use it.

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This is required for the panel to work on bcm911360, where CLCDCLK is
the fixed 200Mhz AXI41 clock.  The rate set is still passed up to the
CLCDCLK, for platforms that have a settable rate on that one.

v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
    COMMON_CLK.
v3: Mark the clk_ops static (caught by Stephen).

Signed-off-by: Eric Anholt <eric@anholt.net>
Link: http://patchwork.freedesktop.org/patch/msgid/20170508193348.30236-1-eric@anholt.net
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Eric Anholt
2017-05-08 12:33:48 -07:00
parent 2098105ec6
commit 032838f9cb
5 changed files with 163 additions and 24 deletions
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1
drivers/gpu/drm/pl111/Kconfig
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@@ -2,6 +2,7 @@ config DRM_PL111
tristate "DRM Support for PL111 CLCD Controller"
depends on DRM
depends on ARM || ARM64 || COMPILE_TEST
depends on COMMON_CLK
select DRM_KMS_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER