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ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC

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mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai
2016-01-21 13:26:41 +08:00
committed by Maxime Ripard
parent 675ec62b08
commit 02df9cb85e
1 changed files with 6 additions and 0 deletions
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6
arch/arm/boot/dts/sun9i-a80-optimus.dts
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@@ -174,9 +174,15 @@
vmmc-supply = <&reg_vcc3v0>; vmmc-supply = <&reg_vcc3v0>;
bus-width = <8>; bus-width = <8>;
non-removable; non-removable;
cap-mmc-hw-reset;
status = "okay"; status = "okay";
}; };
&mmc2_8bit_pins {
/* Increase drive strength for DDR modes */
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
};
&reg_usb1_vbus { &reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_optimus>; pinctrl-0 = <&usb1_vbus_pin_optimus>;
gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */