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MIPS: mm: c-r4k: Detect instruction cache aliases

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The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras
2014-01-30 17:21:29 +00:00
committed by Ralf Baechle
parent 0414855fdc
commit 02dc6bfb08
2 changed files with 11 additions and 3 deletions
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3
arch/mips/include/asm/mipsregs.h
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@@ -653,6 +653,9 @@
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
/* EntryHI bit definition */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)