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drm/amd/powerplay: revise the way to retrieve the board parameters

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It can support different NV1x ASIC better. And this can guard
no member got missing.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
2020-03-06 17:54:44 +08:00
committed by Alex Deucher
parent ced1ba9761
commit 02c0bb4ee3
2 changed files with 128 additions and 69 deletions
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102
drivers/gpu/drm/amd/include/atomfirmware.h
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@@ -1876,6 +1876,108 @@ struct atom_smc_dpm_info_v4_6
uint32_t boardreserved[10];
};
struct atom_smc_dpm_info_v4_7
{
struct atom_common_table_header table_header;
// SECTION: BOARD PARAMETERS
// I2C Control
struct smudpm_i2c_controller_config_v2 I2cControllers[8];
// SVI2 Board Parameters
uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
uint8_t Padding8_V;
// Telemetry Settings
uint16_t GfxMaxCurrent; // in Amps
uint8_t GfxOffset; // in Amps
uint8_t Padding_TelemetryGfx;
uint16_t SocMaxCurrent; // in Amps
uint8_t SocOffset; // in Amps
uint8_t Padding_TelemetrySoc;
uint16_t Mem0MaxCurrent; // in Amps
uint8_t Mem0Offset; // in Amps
uint8_t Padding_TelemetryMem0;
uint16_t Mem1MaxCurrent; // in Amps
uint8_t Mem1Offset; // in Amps
uint8_t Padding_TelemetryMem1;
// GPIO Settings
uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
uint8_t GthrGpio; // GPIO pin configured for GTHR Event
uint8_t GthrPolarity; // replace GPIO polarity for GTHR
// LED Display Settings
uint8_t LedPin0; // GPIO number for LedPin[0]
uint8_t LedPin1; // GPIO number for LedPin[1]
uint8_t LedPin2; // GPIO number for LedPin[2]
uint8_t padding8_4;
// GFXCLK PLL Spread Spectrum
uint8_t PllGfxclkSpreadEnabled; // on or off
uint8_t PllGfxclkSpreadPercent; // Q4.4
uint16_t PllGfxclkSpreadFreq; // kHz
// GFXCLK DFLL Spread Spectrum
uint8_t DfllGfxclkSpreadEnabled; // on or off
uint8_t DfllGfxclkSpreadPercent; // Q4.4
uint16_t DfllGfxclkSpreadFreq; // kHz
// UCLK Spread Spectrum
uint8_t UclkSpreadEnabled; // on or off
uint8_t UclkSpreadPercent; // Q4.4
uint16_t UclkSpreadFreq; // kHz
// SOCCLK Spread Spectrum
uint8_t SoclkSpreadEnabled; // on or off
uint8_t SocclkSpreadPercent; // Q4.4
uint16_t SocclkSpreadFreq; // kHz
// Total board power
uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
uint16_t BoardPadding;
// Mvdd Svi2 Div Ratio Setting
uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
// GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
uint8_t GpioI2cScl; // Serial Clock
uint8_t GpioI2cSda; // Serial Data
uint16_t GpioPadding;
// Additional LED Display Settings
uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
uint16_t LedEnableMask;
// Power Limit Scalars
uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
uint8_t MvddUlvPhaseSheddingMask;
uint8_t VddciUlvPhaseSheddingMask;
uint8_t Padding8_Psi1;
uint8_t Padding8_Psi2;
uint32_t BoardReserved[5];
};
/*
***************************************************************************
Data Table asic_profiling_info structure