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clk: samsung: exynos5420: update clocks for GSCL and MSCL blocks

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This patch adds the missing GSCL and MSCL block clocks
and corrects some wrong parent-child relationships.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This commit is contained in:
Shaik Ameer Basha
2014-05-08 16:57:52 +05:30
committed by Tomasz Figa
parent 3a767b35c6
commit 02932381ca
2 changed files with 46 additions and 27 deletions
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4
include/dt-bindings/clock/exynos5420.h
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@@ -159,7 +159,7 @@
#define CLK_GSCL_WB 464
#define CLK_GSCL0 465
#define CLK_GSCL1 466
#define CLK_CLK_3AA 467
#define CLK_FIMC_3AA 467
#define CLK_ACLK266_G2D 470
#define CLK_SSS 471
#define CLK_SLIM_SSS 472
@@ -172,6 +172,8 @@
#define CLK_SMMU_FIMCL1 493
#define CLK_SMMU_FIMCL3 494
#define CLK_FIMC_LITE3 495
#define CLK_FIMC_LITE0 496
#define CLK_FIMC_LITE1 497
#define CLK_ACLK_G3D 500
#define CLK_G3D 501
#define CLK_SMMU_MIXER 502