gma500: initial medfield merge
We need to merge this ahead of some of the cleanup because a lot of needed cleanup spans both new and old chips. If we try and clean up and the merge we end up fighting ourselves. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> [With a load of the cleanup stuff folded in, register stuff reworked sanely] Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Este cometimento está contido em:
Kirill A. Shutemov
cometido por
Dave Airlie
Dave Airlie
ascendente
c6265ff593
cometimento
026abc3332
691
drivers/gpu/drm/gma500/mdfld_device.c
Ficheiro normal
691
drivers/gpu/drm/gma500/mdfld_device.c
Ficheiro normal
@@ -0,0 +1,691 @@
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/**************************************************************************
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* Copyright (c) 2011, Intel Corporation.
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* All Rights Reserved.
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*
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||||
* This program is free software; you can redistribute it and/or modify it
|
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* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
|
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
|
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#include "psb_drv.h"
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#include "mid_bios.h"
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#include "mdfld_output.h"
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#include "mdfld_dsi_output.h"
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#include "tc35876x-dsi-lvds.h"
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#include <asm/intel_scu_ipc.h>
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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|
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#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
|
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#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
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#define BLC_PWM_FREQ_CALC_CONSTANT 32
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#define MHz 1000000
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#define BRIGHTNESS_MIN_LEVEL 1
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#define BRIGHTNESS_MAX_LEVEL 100
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#define BRIGHTNESS_MASK 0xFF
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#define BLC_POLARITY_NORMAL 0
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#define BLC_POLARITY_INVERSE 1
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#define BLC_ADJUSTMENT_MAX 100
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#define MDFLD_BLC_PWM_PRECISION_FACTOR 10
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#define MDFLD_BLC_MAX_PWM_REG_FREQ 0xFFFE
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#define MDFLD_BLC_MIN_PWM_REG_FREQ 0x2
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#define MDFLD_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
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#define MDFLD_BACKLIGHT_PWM_CTL_SHIFT (16)
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static struct backlight_device *mdfld_backlight_device;
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int mdfld_set_brightness(struct backlight_device *bd)
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{
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struct drm_device *dev =
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(struct drm_device *)bl_get_data(mdfld_backlight_device);
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struct drm_psb_private *dev_priv = dev->dev_private;
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int level = bd->props.brightness;
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DRM_DEBUG_DRIVER("backlight level set to %d\n", level);
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/* Perform value bounds checking */
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if (level < BRIGHTNESS_MIN_LEVEL)
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level = BRIGHTNESS_MIN_LEVEL;
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if (gma_power_begin(dev, false)) {
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u32 adjusted_level = 0;
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/*
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* Adjust the backlight level with the percent in
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* dev_priv->blc_adj2
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*/
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adjusted_level = level * dev_priv->blc_adj2;
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adjusted_level = adjusted_level / BLC_ADJUSTMENT_MAX;
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dev_priv->brightness_adjusted = adjusted_level;
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if (mdfld_get_panel_type(dev, 0) == TC35876X) {
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if (dev_priv->dpi_panel_on[0] ||
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dev_priv->dpi_panel_on[2])
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tc35876x_brightness_control(dev,
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dev_priv->brightness_adjusted);
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} else {
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if (dev_priv->dpi_panel_on[0])
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mdfld_dsi_brightness_control(dev, 0,
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dev_priv->brightness_adjusted);
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}
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if (dev_priv->dpi_panel_on[2])
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mdfld_dsi_brightness_control(dev, 2,
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dev_priv->brightness_adjusted);
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gma_power_end(dev);
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}
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/* cache the brightness for later use */
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dev_priv->brightness = level;
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return 0;
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}
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int mdfld_get_brightness(struct backlight_device *bd)
|
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{
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struct drm_device *dev =
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(struct drm_device *)bl_get_data(mdfld_backlight_device);
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struct drm_psb_private *dev_priv = dev->dev_private;
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DRM_DEBUG_DRIVER("brightness = 0x%x \n", dev_priv->brightness);
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/* return locally cached var instead of HW read (due to DPST etc.) */
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return dev_priv->brightness;
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}
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static const struct backlight_ops mdfld_ops = {
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.get_brightness = mdfld_get_brightness,
|
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.update_status = mdfld_set_brightness,
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};
|
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|
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static int device_backlight_init(struct drm_device *dev)
|
||||
{
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struct drm_psb_private *dev_priv = (struct drm_psb_private *)
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dev->dev_private;
|
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dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
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dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
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return 0;
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}
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int mdfld_backlight_init(struct drm_device *dev)
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{
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struct backlight_properties props;
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int ret = 0;
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memset(&props, 0, sizeof(struct backlight_properties));
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props.max_brightness = BRIGHTNESS_MAX_LEVEL;
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props.type = BACKLIGHT_PLATFORM;
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mdfld_backlight_device = backlight_device_register("mdfld-bl",
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NULL, (void *)dev, &mdfld_ops, &props);
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if (IS_ERR(mdfld_backlight_device))
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return PTR_ERR(mdfld_backlight_device);
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ret = device_backlight_init(dev);
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if (ret)
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return ret;
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mdfld_backlight_device->props.brightness = BRIGHTNESS_MAX_LEVEL;
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mdfld_backlight_device->props.max_brightness = BRIGHTNESS_MAX_LEVEL;
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backlight_update_status(mdfld_backlight_device);
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return 0;
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}
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#endif
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struct backlight_device *mdfld_get_backlight_device(void)
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{
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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return mdfld_backlight_device;
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#else
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return NULL;
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#endif
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}
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/*
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* mdfld_save_display_registers
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*
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* Description: We are going to suspend so save current display
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* register state.
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*
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* Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio
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*/
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static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct medfield_state *regs = &dev_priv->regs.mdfld;
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int i;
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/* register */
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u32 dpll_reg = MRST_DPLL_A;
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u32 fp_reg = MRST_FPA0;
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u32 pipeconf_reg = PIPEACONF;
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u32 htot_reg = HTOTAL_A;
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u32 hblank_reg = HBLANK_A;
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u32 hsync_reg = HSYNC_A;
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u32 vtot_reg = VTOTAL_A;
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u32 vblank_reg = VBLANK_A;
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u32 vsync_reg = VSYNC_A;
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u32 pipesrc_reg = PIPEASRC;
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u32 dspstride_reg = DSPASTRIDE;
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u32 dsplinoff_reg = DSPALINOFF;
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u32 dsptileoff_reg = DSPATILEOFF;
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u32 dspsize_reg = DSPASIZE;
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u32 dsppos_reg = DSPAPOS;
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u32 dspsurf_reg = DSPASURF;
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u32 mipi_reg = MIPI;
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u32 dspcntr_reg = DSPACNTR;
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u32 dspstatus_reg = PIPEASTAT;
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u32 palette_reg = PALETTE_A;
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/* pointer to values */
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u32 *dpll_val = ®s->saveDPLL_A;
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u32 *fp_val = ®s->saveFPA0;
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u32 *pipeconf_val = ®s->savePIPEACONF;
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u32 *htot_val = ®s->saveHTOTAL_A;
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u32 *hblank_val = ®s->saveHBLANK_A;
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u32 *hsync_val = ®s->saveHSYNC_A;
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u32 *vtot_val = ®s->saveVTOTAL_A;
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u32 *vblank_val = ®s->saveVBLANK_A;
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u32 *vsync_val = ®s->saveVSYNC_A;
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u32 *pipesrc_val = ®s->savePIPEASRC;
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u32 *dspstride_val = ®s->saveDSPASTRIDE;
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u32 *dsplinoff_val = ®s->saveDSPALINOFF;
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u32 *dsptileoff_val = ®s->saveDSPATILEOFF;
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u32 *dspsize_val = ®s->saveDSPASIZE;
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u32 *dsppos_val = ®s->saveDSPAPOS;
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u32 *dspsurf_val = ®s->saveDSPASURF;
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u32 *mipi_val = ®s->saveMIPI;
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u32 *dspcntr_val = ®s->saveDSPACNTR;
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u32 *dspstatus_val = ®s->saveDSPASTATUS;
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u32 *palette_val = regs->save_palette_a;
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switch (pipe) {
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case 0:
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break;
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case 1:
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/* regester */
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dpll_reg = MDFLD_DPLL_B;
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fp_reg = MDFLD_DPLL_DIV0;
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pipeconf_reg = PIPEBCONF;
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htot_reg = HTOTAL_B;
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hblank_reg = HBLANK_B;
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hsync_reg = HSYNC_B;
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vtot_reg = VTOTAL_B;
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vblank_reg = VBLANK_B;
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vsync_reg = VSYNC_B;
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pipesrc_reg = PIPEBSRC;
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dspstride_reg = DSPBSTRIDE;
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dsplinoff_reg = DSPBLINOFF;
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dsptileoff_reg = DSPBTILEOFF;
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dspsize_reg = DSPBSIZE;
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dsppos_reg = DSPBPOS;
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dspsurf_reg = DSPBSURF;
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dspcntr_reg = DSPBCNTR;
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dspstatus_reg = PIPEBSTAT;
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palette_reg = PALETTE_B;
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/* values */
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dpll_val = ®s->saveDPLL_B;
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fp_val = ®s->saveFPB0;
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pipeconf_val = ®s->savePIPEBCONF;
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htot_val = ®s->saveHTOTAL_B;
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hblank_val = ®s->saveHBLANK_B;
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hsync_val = ®s->saveHSYNC_B;
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vtot_val = ®s->saveVTOTAL_B;
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vblank_val = ®s->saveVBLANK_B;
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vsync_val = ®s->saveVSYNC_B;
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pipesrc_val = ®s->savePIPEBSRC;
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dspstride_val = ®s->saveDSPBSTRIDE;
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dsplinoff_val = ®s->saveDSPBLINOFF;
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dsptileoff_val = ®s->saveDSPBTILEOFF;
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dspsize_val = ®s->saveDSPBSIZE;
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dsppos_val = ®s->saveDSPBPOS;
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dspsurf_val = ®s->saveDSPBSURF;
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dspcntr_val = ®s->saveDSPBCNTR;
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dspstatus_val = ®s->saveDSPBSTATUS;
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palette_val = regs->save_palette_b;
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break;
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case 2:
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/* register */
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pipeconf_reg = PIPECCONF;
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htot_reg = HTOTAL_C;
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hblank_reg = HBLANK_C;
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hsync_reg = HSYNC_C;
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vtot_reg = VTOTAL_C;
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vblank_reg = VBLANK_C;
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vsync_reg = VSYNC_C;
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pipesrc_reg = PIPECSRC;
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dspstride_reg = DSPCSTRIDE;
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dsplinoff_reg = DSPCLINOFF;
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dsptileoff_reg = DSPCTILEOFF;
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dspsize_reg = DSPCSIZE;
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dsppos_reg = DSPCPOS;
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dspsurf_reg = DSPCSURF;
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mipi_reg = MIPI_C;
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dspcntr_reg = DSPCCNTR;
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dspstatus_reg = PIPECSTAT;
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palette_reg = PALETTE_C;
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/* pointer to values */
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pipeconf_val = ®s->savePIPECCONF;
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htot_val = ®s->saveHTOTAL_C;
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hblank_val = ®s->saveHBLANK_C;
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hsync_val = ®s->saveHSYNC_C;
|
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vtot_val = ®s->saveVTOTAL_C;
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vblank_val = ®s->saveVBLANK_C;
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vsync_val = ®s->saveVSYNC_C;
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pipesrc_val = ®s->savePIPECSRC;
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dspstride_val = ®s->saveDSPCSTRIDE;
|
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dsplinoff_val = ®s->saveDSPCLINOFF;
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dsptileoff_val = ®s->saveDSPCTILEOFF;
|
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dspsize_val = ®s->saveDSPCSIZE;
|
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dsppos_val = ®s->saveDSPCPOS;
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dspsurf_val = ®s->saveDSPCSURF;
|
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mipi_val = ®s->saveMIPI_C;
|
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dspcntr_val = ®s->saveDSPCCNTR;
|
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dspstatus_val = ®s->saveDSPCSTATUS;
|
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palette_val = regs->save_palette_c;
|
||||
break;
|
||||
default:
|
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DRM_ERROR("%s, invalid pipe number.\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Pipe & plane A info */
|
||||
*dpll_val = PSB_RVDC32(dpll_reg);
|
||||
*fp_val = PSB_RVDC32(fp_reg);
|
||||
*pipeconf_val = PSB_RVDC32(pipeconf_reg);
|
||||
*htot_val = PSB_RVDC32(htot_reg);
|
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*hblank_val = PSB_RVDC32(hblank_reg);
|
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*hsync_val = PSB_RVDC32(hsync_reg);
|
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*vtot_val = PSB_RVDC32(vtot_reg);
|
||||
*vblank_val = PSB_RVDC32(vblank_reg);
|
||||
*vsync_val = PSB_RVDC32(vsync_reg);
|
||||
*pipesrc_val = PSB_RVDC32(pipesrc_reg);
|
||||
*dspstride_val = PSB_RVDC32(dspstride_reg);
|
||||
*dsplinoff_val = PSB_RVDC32(dsplinoff_reg);
|
||||
*dsptileoff_val = PSB_RVDC32(dsptileoff_reg);
|
||||
*dspsize_val = PSB_RVDC32(dspsize_reg);
|
||||
*dsppos_val = PSB_RVDC32(dsppos_reg);
|
||||
*dspsurf_val = PSB_RVDC32(dspsurf_reg);
|
||||
*dspcntr_val = PSB_RVDC32(dspcntr_reg);
|
||||
*dspstatus_val = PSB_RVDC32(dspstatus_reg);
|
||||
|
||||
/*save palette (gamma) */
|
||||
for (i = 0; i < 256; i++)
|
||||
palette_val[i] = PSB_RVDC32(palette_reg + (i << 2));
|
||||
|
||||
if (pipe == 1) {
|
||||
regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
|
||||
regs->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
|
||||
|
||||
regs->saveHDMIPHYMISCCTL = PSB_RVDC32(HDMIPHYMISCCTL);
|
||||
regs->saveHDMIB_CONTROL = PSB_RVDC32(HDMIB_CONTROL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
*mipi_val = PSB_RVDC32(mipi_reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* mdfld_restore_display_registers
|
||||
*
|
||||
* Description: We are going to resume so restore display register state.
|
||||
*
|
||||
* Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio
|
||||
*/
|
||||
static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
|
||||
{
|
||||
/* To get panel out of ULPS mode. */
|
||||
u32 temp = 0;
|
||||
u32 device_ready_reg = DEVICE_READY_REG;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct mdfld_dsi_config *dsi_config = NULL;
|
||||
struct medfield_state *regs = &dev_priv->regs.mdfld;
|
||||
u32 i = 0;
|
||||
u32 dpll = 0;
|
||||
u32 timeout = 0;
|
||||
|
||||
/* regester */
|
||||
u32 dpll_reg = MRST_DPLL_A;
|
||||
u32 fp_reg = MRST_FPA0;
|
||||
u32 pipeconf_reg = PIPEACONF;
|
||||
u32 htot_reg = HTOTAL_A;
|
||||
u32 hblank_reg = HBLANK_A;
|
||||
u32 hsync_reg = HSYNC_A;
|
||||
u32 vtot_reg = VTOTAL_A;
|
||||
u32 vblank_reg = VBLANK_A;
|
||||
u32 vsync_reg = VSYNC_A;
|
||||
u32 pipesrc_reg = PIPEASRC;
|
||||
u32 dspstride_reg = DSPASTRIDE;
|
||||
u32 dsplinoff_reg = DSPALINOFF;
|
||||
u32 dsptileoff_reg = DSPATILEOFF;
|
||||
u32 dspsize_reg = DSPASIZE;
|
||||
u32 dsppos_reg = DSPAPOS;
|
||||
u32 dspsurf_reg = DSPASURF;
|
||||
u32 dspstatus_reg = PIPEASTAT;
|
||||
u32 mipi_reg = MIPI;
|
||||
u32 dspcntr_reg = DSPACNTR;
|
||||
u32 palette_reg = PALETTE_A;
|
||||
|
||||
/* values */
|
||||
u32 dpll_val = regs->saveDPLL_A & ~DPLL_VCO_ENABLE;
|
||||
u32 fp_val = regs->saveFPA0;
|
||||
u32 pipeconf_val = regs->savePIPEACONF;
|
||||
u32 htot_val = regs->saveHTOTAL_A;
|
||||
u32 hblank_val = regs->saveHBLANK_A;
|
||||
u32 hsync_val = regs->saveHSYNC_A;
|
||||
u32 vtot_val = regs->saveVTOTAL_A;
|
||||
u32 vblank_val = regs->saveVBLANK_A;
|
||||
u32 vsync_val = regs->saveVSYNC_A;
|
||||
u32 pipesrc_val = regs->savePIPEASRC;
|
||||
u32 dspstride_val = regs->saveDSPASTRIDE;
|
||||
u32 dsplinoff_val = regs->saveDSPALINOFF;
|
||||
u32 dsptileoff_val = regs->saveDSPATILEOFF;
|
||||
u32 dspsize_val = regs->saveDSPASIZE;
|
||||
u32 dsppos_val = regs->saveDSPAPOS;
|
||||
u32 dspsurf_val = regs->saveDSPASURF;
|
||||
u32 dspstatus_val = regs->saveDSPASTATUS;
|
||||
u32 mipi_val = regs->saveMIPI;
|
||||
u32 dspcntr_val = regs->saveDSPACNTR;
|
||||
u32 *palette_val = regs->save_palette_a;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
dsi_config = dev_priv->dsi_configs[0];
|
||||
break;
|
||||
case 1:
|
||||
/* regester */
|
||||
dpll_reg = MDFLD_DPLL_B;
|
||||
fp_reg = MDFLD_DPLL_DIV0;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
htot_reg = HTOTAL_B;
|
||||
hblank_reg = HBLANK_B;
|
||||
hsync_reg = HSYNC_B;
|
||||
vtot_reg = VTOTAL_B;
|
||||
vblank_reg = VBLANK_B;
|
||||
vsync_reg = VSYNC_B;
|
||||
pipesrc_reg = PIPEBSRC;
|
||||
dspstride_reg = DSPBSTRIDE;
|
||||
dsplinoff_reg = DSPBLINOFF;
|
||||
dsptileoff_reg = DSPBTILEOFF;
|
||||
dspsize_reg = DSPBSIZE;
|
||||
dsppos_reg = DSPBPOS;
|
||||
dspsurf_reg = DSPBSURF;
|
||||
dspcntr_reg = DSPBCNTR;
|
||||
dspstatus_reg = PIPEBSTAT;
|
||||
palette_reg = PALETTE_B;
|
||||
|
||||
/* values */
|
||||
dpll_val = regs->saveDPLL_B & ~DPLL_VCO_ENABLE;
|
||||
fp_val = regs->saveFPB0;
|
||||
pipeconf_val = regs->savePIPEBCONF;
|
||||
htot_val = regs->saveHTOTAL_B;
|
||||
hblank_val = regs->saveHBLANK_B;
|
||||
hsync_val = regs->saveHSYNC_B;
|
||||
vtot_val = regs->saveVTOTAL_B;
|
||||
vblank_val = regs->saveVBLANK_B;
|
||||
vsync_val = regs->saveVSYNC_B;
|
||||
pipesrc_val = regs->savePIPEBSRC;
|
||||
dspstride_val = regs->saveDSPBSTRIDE;
|
||||
dsplinoff_val = regs->saveDSPBLINOFF;
|
||||
dsptileoff_val = regs->saveDSPBTILEOFF;
|
||||
dspsize_val = regs->saveDSPBSIZE;
|
||||
dsppos_val = regs->saveDSPBPOS;
|
||||
dspsurf_val = regs->saveDSPBSURF;
|
||||
dspcntr_val = regs->saveDSPBCNTR;
|
||||
dspstatus_val = regs->saveDSPBSTATUS;
|
||||
palette_val = regs->save_palette_b;
|
||||
break;
|
||||
case 2:
|
||||
/* regester */
|
||||
pipeconf_reg = PIPECCONF;
|
||||
htot_reg = HTOTAL_C;
|
||||
hblank_reg = HBLANK_C;
|
||||
hsync_reg = HSYNC_C;
|
||||
vtot_reg = VTOTAL_C;
|
||||
vblank_reg = VBLANK_C;
|
||||
vsync_reg = VSYNC_C;
|
||||
pipesrc_reg = PIPECSRC;
|
||||
dspstride_reg = DSPCSTRIDE;
|
||||
dsplinoff_reg = DSPCLINOFF;
|
||||
dsptileoff_reg = DSPCTILEOFF;
|
||||
dspsize_reg = DSPCSIZE;
|
||||
dsppos_reg = DSPCPOS;
|
||||
dspsurf_reg = DSPCSURF;
|
||||
mipi_reg = MIPI_C;
|
||||
dspcntr_reg = DSPCCNTR;
|
||||
dspstatus_reg = PIPECSTAT;
|
||||
palette_reg = PALETTE_C;
|
||||
|
||||
/* values */
|
||||
pipeconf_val = regs->savePIPECCONF;
|
||||
htot_val = regs->saveHTOTAL_C;
|
||||
hblank_val = regs->saveHBLANK_C;
|
||||
hsync_val = regs->saveHSYNC_C;
|
||||
vtot_val = regs->saveVTOTAL_C;
|
||||
vblank_val = regs->saveVBLANK_C;
|
||||
vsync_val = regs->saveVSYNC_C;
|
||||
pipesrc_val = regs->savePIPECSRC;
|
||||
dspstride_val = regs->saveDSPCSTRIDE;
|
||||
dsplinoff_val = regs->saveDSPCLINOFF;
|
||||
dsptileoff_val = regs->saveDSPCTILEOFF;
|
||||
dspsize_val = regs->saveDSPCSIZE;
|
||||
dsppos_val = regs->saveDSPCPOS;
|
||||
dspsurf_val = regs->saveDSPCSURF;
|
||||
mipi_val = regs->saveMIPI_C;
|
||||
dspcntr_val = regs->saveDSPCCNTR;
|
||||
dspstatus_val = regs->saveDSPCSTATUS;
|
||||
palette_val = regs->save_palette_c;
|
||||
|
||||
dsi_config = dev_priv->dsi_configs[1];
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("%s, invalid pipe number.\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*make sure VGA plane is off. it initializes to on after reset!*/
|
||||
PSB_WVDC32(0x80000000, VGACNTRL);
|
||||
|
||||
if (pipe == 1) {
|
||||
PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg);
|
||||
PSB_RVDC32(dpll_reg);
|
||||
|
||||
PSB_WVDC32(fp_val, fp_reg);
|
||||
} else {
|
||||
|
||||
dpll = PSB_RVDC32(dpll_reg);
|
||||
|
||||
if (!(dpll & DPLL_VCO_ENABLE)) {
|
||||
|
||||
/* When ungating power of DPLL, needs to wait 0.5us
|
||||
before enable the VCO */
|
||||
if (dpll & MDFLD_PWR_GATE_EN) {
|
||||
dpll &= ~MDFLD_PWR_GATE_EN;
|
||||
PSB_WVDC32(dpll, dpll_reg);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
PSB_WVDC32(fp_val, fp_reg);
|
||||
PSB_WVDC32(dpll_val, dpll_reg);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
|
||||
dpll_val |= DPLL_VCO_ENABLE;
|
||||
PSB_WVDC32(dpll_val, dpll_reg);
|
||||
PSB_RVDC32(dpll_reg);
|
||||
|
||||
/* wait for DSI PLL to lock */
|
||||
while (timeout < 20000 &&
|
||||
!(PSB_RVDC32(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) {
|
||||
udelay(150);
|
||||
timeout++;
|
||||
}
|
||||
|
||||
if (timeout == 20000) {
|
||||
DRM_ERROR("%s, can't lock DSIPLL.\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Restore mode */
|
||||
PSB_WVDC32(htot_val, htot_reg);
|
||||
PSB_WVDC32(hblank_val, hblank_reg);
|
||||
PSB_WVDC32(hsync_val, hsync_reg);
|
||||
PSB_WVDC32(vtot_val, vtot_reg);
|
||||
PSB_WVDC32(vblank_val, vblank_reg);
|
||||
PSB_WVDC32(vsync_val, vsync_reg);
|
||||
PSB_WVDC32(pipesrc_val, pipesrc_reg);
|
||||
PSB_WVDC32(dspstatus_val, dspstatus_reg);
|
||||
|
||||
/*set up the plane*/
|
||||
PSB_WVDC32(dspstride_val, dspstride_reg);
|
||||
PSB_WVDC32(dsplinoff_val, dsplinoff_reg);
|
||||
PSB_WVDC32(dsptileoff_val, dsptileoff_reg);
|
||||
PSB_WVDC32(dspsize_val, dspsize_reg);
|
||||
PSB_WVDC32(dsppos_val, dsppos_reg);
|
||||
PSB_WVDC32(dspsurf_val, dspsurf_reg);
|
||||
|
||||
if (pipe == 1) {
|
||||
/* restore palette (gamma) */
|
||||
/*DRM_UDELAY(50000); */
|
||||
for (i = 0; i < 256; i++)
|
||||
PSB_WVDC32(palette_val[i], palette_reg + (i << 2));
|
||||
|
||||
PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL);
|
||||
PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
|
||||
|
||||
/*TODO: resume HDMI port */
|
||||
|
||||
/*TODO: resume pipe*/
|
||||
|
||||
/*enable the plane*/
|
||||
PSB_WVDC32(dspcntr_val & ~DISPLAY_PLANE_ENABLE, dspcntr_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*set up pipe related registers*/
|
||||
PSB_WVDC32(mipi_val, mipi_reg);
|
||||
|
||||
/*setup MIPI adapter + MIPI IP registers*/
|
||||
if (dsi_config)
|
||||
mdfld_dsi_controller_init(dsi_config, pipe);
|
||||
|
||||
if (in_atomic() || in_interrupt())
|
||||
mdelay(20);
|
||||
else
|
||||
msleep(20);
|
||||
|
||||
/*enable the plane*/
|
||||
PSB_WVDC32(dspcntr_val, dspcntr_reg);
|
||||
|
||||
if (in_atomic() || in_interrupt())
|
||||
mdelay(20);
|
||||
else
|
||||
msleep(20);
|
||||
|
||||
/* LP Hold Release */
|
||||
temp = REG_READ(mipi_reg);
|
||||
temp |= LP_OUTPUT_HOLD_RELEASE;
|
||||
REG_WRITE(mipi_reg, temp);
|
||||
mdelay(1);
|
||||
|
||||
|
||||
/* Set DSI host to exit from Utra Low Power State */
|
||||
temp = REG_READ(device_ready_reg);
|
||||
temp &= ~ULPS_MASK;
|
||||
temp |= 0x3;
|
||||
temp |= EXIT_ULPS_DEV_READY;
|
||||
REG_WRITE(device_ready_reg, temp);
|
||||
mdelay(1);
|
||||
|
||||
temp = REG_READ(device_ready_reg);
|
||||
temp &= ~ULPS_MASK;
|
||||
temp |= EXITING_ULPS;
|
||||
REG_WRITE(device_ready_reg, temp);
|
||||
mdelay(1);
|
||||
|
||||
/*enable the pipe*/
|
||||
PSB_WVDC32(pipeconf_val, pipeconf_reg);
|
||||
|
||||
/* restore palette (gamma) */
|
||||
/*DRM_UDELAY(50000); */
|
||||
for (i = 0; i < 256; i++)
|
||||
PSB_WVDC32(palette_val[i], palette_reg + (i << 2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mdfld_save_registers(struct drm_device *dev)
|
||||
{
|
||||
/* mdfld_save_cursor_overlay_registers(dev); */
|
||||
mdfld_save_display_registers(dev, 0);
|
||||
mdfld_save_display_registers(dev, 2);
|
||||
mdfld_disable_crtc(dev, 0);
|
||||
mdfld_disable_crtc(dev, 2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mdfld_restore_registers(struct drm_device *dev)
|
||||
{
|
||||
mdfld_restore_display_registers(dev, 2);
|
||||
mdfld_restore_display_registers(dev, 0);
|
||||
/* mdfld_restore_cursor_overlay_registers(dev); */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mdfld_power_down(struct drm_device *dev)
|
||||
{
|
||||
/* FIXME */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mdfld_power_up(struct drm_device *dev)
|
||||
{
|
||||
/* FIXME */
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct psb_ops mdfld_chip_ops = {
|
||||
.name = "mdfld",
|
||||
.accel_2d = 0,
|
||||
.pipes = 3,
|
||||
.crtcs = 3,
|
||||
.sgx_offset = MRST_SGX_OFFSET,
|
||||
|
||||
.chip_setup = mid_chip_setup,
|
||||
.crtc_helper = &mdfld_helper_funcs,
|
||||
.crtc_funcs = &psb_intel_crtc_funcs,
|
||||
|
||||
.output_init = mdfld_output_init,
|
||||
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
.backlight_init = mdfld_backlight_init,
|
||||
#endif
|
||||
|
||||
.save_regs = mdfld_save_registers,
|
||||
.restore_regs = mdfld_restore_registers,
|
||||
.power_down = mdfld_power_down,
|
||||
.power_up = mdfld_power_up,
|
||||
};
|
||||
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