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xhci: Wait until link state trainsits to U0 after setting USB_SS_PORT_LS_U0

소스 검색 
Like U3 case, xHCI spec doesn't specify the upper bound of U0 transition
time. The 20ms is not enough for some devices.

Intead of polling PLS or PLC, we can facilitate the port change event to
know that the link transits to U0 is completed.

While at it, also separate U0 and U3 case to make the code cleaner.

[variable rename to u3exit, and skip completion for usb2 ports -Mathias ]
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20200312144517.1593-8-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Kai-Heng Feng
2020-03-12 16:45:15 +02:00
committed by Greg Kroah-Hartman
부모 eb002726fa
커밋 0200b9f790
4개의 변경된 파일과 34개의 추가작업 그리고 13개의 파일을 삭제
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44
drivers/usb/host/xhci-hub.c
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@@ -1308,7 +1308,33 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
wIndex, link_state);
goto error;
}
if (link_state == USB_SS_PORT_LS_U0) {
if ((temp & PORT_PLS_MASK) == XDEV_U0)
break;
if (!((temp & PORT_PLS_MASK) == XDEV_U1 ||
(temp & PORT_PLS_MASK) == XDEV_U2 ||
(temp & PORT_PLS_MASK) == XDEV_U3)) {
xhci_warn(xhci, "Can only set port %d to U0 from U state\n",
wIndex);
goto error;
}
reinit_completion(&bus_state->u3exit_done[wIndex]);
xhci_set_link_state(xhci, ports[wIndex],
USB_SS_PORT_LS_U0);
spin_unlock_irqrestore(&xhci->lock, flags);
if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
msecs_to_jiffies(100)))
xhci_dbg(xhci, "missing U0 port change event for port %d\n",
wIndex);
spin_lock_irqsave(&xhci->lock, flags);
temp = readl(ports[wIndex]->addr);
break;
}
if (link_state == USB_SS_PORT_LS_U3) {
int retries = 16;
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
wIndex + 1);
if (slot_id) {
@@ -1319,26 +1345,18 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
xhci_stop_device(xhci, slot_id, 1);
spin_lock_irqsave(&xhci->lock, flags);
}
}
xhci_set_link_state(xhci, ports[wIndex], link_state);
spin_unlock_irqrestore(&xhci->lock, flags);
if (link_state == USB_SS_PORT_LS_U3) {
int retries = 16;
xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
spin_unlock_irqrestore(&xhci->lock, flags);
while (retries--) {
usleep_range(4000, 8000);
temp = readl(ports[wIndex]->addr);
if ((temp & PORT_PLS_MASK) == XDEV_U3)
break;
}
}
spin_lock_irqsave(&xhci->lock, flags);
temp = readl(ports[wIndex]->addr);
if (link_state == USB_SS_PORT_LS_U3)
spin_lock_irqsave(&xhci->lock, flags);
temp = readl(ports[wIndex]->addr);
bus_state->suspended_ports |= 1 << wIndex;
}
break;
case USB_PORT_FEAT_POWER:
/*