Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs: Reset subsystem, merged through arm-soc by tradition: - Make bool drivers explicitly non-modular - New support for i.MX7 and Arria10 reset controllers PATA driver for Palmchip BK371 (acked by Tejun) Power domain drivers for i.MX (GPC, GPCv2) - Moved out of mach-imx for GPC - Bunch of tweaks, fixes, etc PMC support for Tegra186 SoC detection support for Renesas RZ/G1H and RZ/G1N Move Tegra flow controller driver from mach directory to drivers/soc - (Power management / CPU power driver) Misc smaller tweaks for other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) soc: pm-domain: Fix the mangled urls soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0 soc: renesas: rcar-sysc: Add support for fixing up power area tables soc: renesas: Register SoC device early soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible soc: imx: gpc: add defines for domain index soc: imx: Add GPCv2 power gating driver dt-bindings: Add GPCv2 power gating driver ARM/clk: move the ICST library to drivers/clk ARM: plat-versatile: remove stale clock header ARM: keystone: Drop PM domain support for k2g soc: ti: Add ti_sci_pm_domains driver dt-bindings: Add TI SCI PM Domains PM / Domains: Do not check if simple providers have phandle cells PM / Domains: Add generic data pointer to genpd data struct soc/tegra: Add initial flowctrl support for Tegra132/210 soc/tegra: flowctrl: Add basic platform driver soc/tegra: Move Tegra flowctrl driver ARM: tegra: Remove unnecessary inclusion of flowctrl header ...
This commit is contained in:
Linus Torvalds
@@ -10,26 +10,17 @@
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regulator/consumer.h>
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#include <linux/irqchip/arm-gic.h>
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#include "common.h"
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#include "hardware.h"
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#define GPC_CNTR 0x000
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#define GPC_IMR1 0x008
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#define GPC_PGC_GPU_PDN 0x260
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#define GPC_PGC_GPU_PUPSCR 0x264
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#define GPC_PGC_GPU_PDNSCR 0x268
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#define GPC_PGC_CPU_PDN 0x2a0
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#define GPC_PGC_CPU_PUPSCR 0x2a4
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#define GPC_PGC_CPU_PDNSCR 0x2a8
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@@ -39,18 +30,6 @@
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#define IMR_NUM 4
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#define GPC_MAX_IRQS (IMR_NUM * 32)
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#define GPU_VPU_PUP_REQ BIT(1)
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#define GPU_VPU_PDN_REQ BIT(0)
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#define GPC_CLK_MAX 6
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struct pu_domain {
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struct generic_pm_domain base;
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struct regulator *reg;
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struct clk *clk[GPC_CLK_MAX];
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int num_clks;
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};
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static void __iomem *gpc_base;
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static u32 gpc_wake_irqs[IMR_NUM];
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static u32 gpc_saved_imrs[IMR_NUM];
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@@ -296,199 +275,3 @@ void __init imx_gpc_check_dt(void)
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gpc_base = of_iomap(np, 0);
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}
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}
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static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
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{
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int iso, iso2sw;
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u32 val;
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/* Read ISO and ISO2SW power down delays */
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val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
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iso = val & 0x3f;
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iso2sw = (val >> 8) & 0x3f;
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/* Gate off PU domain when GPU/VPU when powered down */
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writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
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/* Request GPC to power down GPU/VPU */
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val = readl_relaxed(gpc_base + GPC_CNTR);
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val |= GPU_VPU_PDN_REQ;
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writel_relaxed(val, gpc_base + GPC_CNTR);
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/* Wait ISO + ISO2SW IPG clock cycles */
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ndelay((iso + iso2sw) * 1000 / 66);
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}
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static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
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{
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struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
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_imx6q_pm_pu_power_off(genpd);
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if (pu->reg)
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regulator_disable(pu->reg);
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return 0;
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}
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static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
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{
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struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
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int i, ret, sw, sw2iso;
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u32 val;
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if (pu->reg)
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ret = regulator_enable(pu->reg);
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if (pu->reg && ret) {
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pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
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return ret;
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}
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/* Enable reset clocks for all devices in the PU domain */
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for (i = 0; i < pu->num_clks; i++)
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clk_prepare_enable(pu->clk[i]);
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/* Gate off PU domain when GPU/VPU when powered down */
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writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
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/* Read ISO and ISO2SW power down delays */
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val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
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sw = val & 0x3f;
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sw2iso = (val >> 8) & 0x3f;
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/* Request GPC to power up GPU/VPU */
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val = readl_relaxed(gpc_base + GPC_CNTR);
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val |= GPU_VPU_PUP_REQ;
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writel_relaxed(val, gpc_base + GPC_CNTR);
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/* Wait ISO + ISO2SW IPG clock cycles */
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ndelay((sw + sw2iso) * 1000 / 66);
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/* Disable reset clocks for all devices in the PU domain */
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for (i = 0; i < pu->num_clks; i++)
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clk_disable_unprepare(pu->clk[i]);
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return 0;
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}
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static struct generic_pm_domain imx6q_arm_domain = {
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.name = "ARM",
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};
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static struct pu_domain imx6q_pu_domain = {
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.base = {
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.name = "PU",
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.power_off = imx6q_pm_pu_power_off,
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.power_on = imx6q_pm_pu_power_on,
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},
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};
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static struct generic_pm_domain imx6sl_display_domain = {
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.name = "DISPLAY",
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};
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static struct generic_pm_domain *imx_gpc_domains[] = {
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&imx6q_arm_domain,
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&imx6q_pu_domain.base,
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&imx6sl_display_domain,
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};
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static struct genpd_onecell_data imx_gpc_onecell_data = {
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.domains = imx_gpc_domains,
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.num_domains = ARRAY_SIZE(imx_gpc_domains),
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};
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static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
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{
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struct clk *clk;
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int i, ret;
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imx6q_pu_domain.reg = pu_reg;
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for (i = 0; ; i++) {
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clk = of_clk_get(dev->of_node, i);
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if (IS_ERR(clk))
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break;
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if (i >= GPC_CLK_MAX) {
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dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
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goto clk_err;
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}
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imx6q_pu_domain.clk[i] = clk;
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}
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imx6q_pu_domain.num_clks = i;
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/* Enable power always in case bootloader disabled it. */
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imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
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if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
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return 0;
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imx6q_pu_domain.base.states = devm_kzalloc(dev,
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sizeof(*imx6q_pu_domain.base.states),
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GFP_KERNEL);
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if (!imx6q_pu_domain.base.states)
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return -ENOMEM;
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imx6q_pu_domain.base.states[0].power_off_latency_ns = 25000;
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imx6q_pu_domain.base.states[0].power_on_latency_ns = 2000000;
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imx6q_pu_domain.base.state_count = 1;
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for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
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pm_genpd_init(imx_gpc_domains[i], NULL, false);
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ret = of_genpd_add_provider_onecell(dev->of_node,
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&imx_gpc_onecell_data);
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if (ret)
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goto power_off;
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return 0;
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power_off:
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imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
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clk_err:
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while (i--)
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clk_put(imx6q_pu_domain.clk[i]);
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imx6q_pu_domain.reg = NULL;
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return -EINVAL;
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}
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static int imx_gpc_probe(struct platform_device *pdev)
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{
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struct regulator *pu_reg;
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int ret;
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/* bail out if DT too old and doesn't provide the necessary info */
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if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
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return 0;
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pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
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if (PTR_ERR(pu_reg) == -ENODEV)
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pu_reg = NULL;
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if (IS_ERR(pu_reg)) {
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ret = PTR_ERR(pu_reg);
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dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
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return ret;
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}
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return imx_gpc_genpd_init(&pdev->dev, pu_reg);
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}
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static const struct of_device_id imx_gpc_dt_ids[] = {
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{ .compatible = "fsl,imx6q-gpc" },
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{ .compatible = "fsl,imx6sl-gpc" },
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{ }
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};
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static struct platform_driver imx_gpc_driver = {
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.driver = {
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.name = "imx-gpc",
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.of_match_table = imx_gpc_dt_ids,
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},
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.probe = imx_gpc_probe,
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};
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static int __init imx_pgc_init(void)
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{
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return platform_driver_register(&imx_gpc_driver);
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}
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subsys_initcall(imx_pgc_init);
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